XR68C681
D.3 Counter/Timer
((- ' '3 % '(% / (
.( . . (% - / (
$' (' ' % + % ((-
%'% % (% ( Figure 9 %% '3 $(- +
'('(& %$(- . %'( + %
((- %'% + .( ' $ &
((- ( $ M/4=N !((&
-(% (% / - = ,% % Table 7 +
(% ( .( $" $
((- %' '% + (% M/4=N .
(% ( ''3 %' -(%% + % %
- ( - + %(% $
'(%
%'(
('(
(($ & /
,% -(%%
" :
#,
5
5*
(($ & /
.(
$ *
14 5%
.DE
,1
M=/N
Figure 9. A Block Diagram of the Circuitry
Associated with the Counter/Timer
Bit 6
Bit 5
Bit 4
C/T Mode
(
(
(
(
Timing Source
2! # #,
5 5 '3 + ' %(
5* 5 '3 + ' * %(
5.:7 # (($$ & /
2! # #,
2! # #," (($$ & /
5.:7 #
5.:7 # (($$ & /
Table 7. ACR[6:4] Bit Field Definition - C/T
@