XR82C684
PB7@Q
47 8
8
8-<=
8
%'(
('(
PBQ
)( 2
% !
P47Q
47 8
8
!PB7@Q
47 8
8!
!P47Q
47 8
8!
Figure 31A. Block Diagram of the Bit Rate Generator portion of the Timing Control Block, for
Channels C and D
D.3 Counter/Timers
((, ) '6 % ' (% 3 . (
-(% -D -D 5' - (%
, . ( 3' 3 (' ' % *
% ((, % '% % (% ( Figure 32
Figure 32A %% '6 (, * '('(&
% (, -D -D# %'(&
%'( * % ((, % '% * -(% D
D ' & 3((, (
P.7@Q P.7@Q# %'(& Please see
4 and 4 for the relationship between the
Counter/Timer mode, the Timing Source and ACR[6:4]
for Counter/Timers #1 and #2, respectively. -
# * -%# (% ( '6 '
,(%% * % % , ( ,
* * %(% '(% Please note that
the QUARTs, packaged in the 44 pin PLCC have limited
options in regards to Timing Source, as depicted in
Table 13 and Table 13A.
90