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XRD5412 View Datasheet(PDF) - Exar Corporation

Part Name
Description
MFG CO.
'XRD5412' PDF : 16 Pages View PDF
1 2 3 4 5 6 7 8 9 10 Next
XRD5408/10/12
TIMING
CS
tCSH0
SCLK
tDS
SDIN
DOUT
tCSS
tCH
tDH
tCL
tD0
Figure 2. Timing Diagram
tCSH1
tCSW
tCS1
1111
1000
1000
0111
0000
Input
1111
0001
0000
1111
0001
(0000)
(0000)
(0000)
(0000)
(0000)
Output
+2
(VREFIN)
255
256
+2
(VREFIN)
129
256
+
2
(VREFIN)
128
256
=
+
VREFIN
+
2
(VREFIN)
127
256
+
2
(VREFIN)
1
256
0000
0000
(0000)
0V
Note:
Write 8-bit data words with four sub-LSB 0s because the DAC input latch
is 12 bits wide.
Table 1. Binary Code Table
Rev. 1.20
6
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