XRD8794AB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRD8794AB' PDF : 24 Pages View PDF
XRD8794AB
DB (0-11)
OE
AIN
MP8791
AP
JP10
PTS
CLOCK
CLOCK
tAP
PTS = AP = OE
DB (0-11)
tDEN
Figure 10. MP8791 Does Not High Z When Clock Is High
Unless OE Is Connected To The Aperture Output Pin
FINAL DESIGN CONSIDERATIONS
After the XRD8794AB has been used to demonstrate that
the XRD8794, the clock timing, and the analog support
circuits are acceptable, the design must be successfully
transferred to the user’s system. A close copy of the
proven layout is recommended as is the use of identical
support devices. Where this is not possible, the following
advice should be heeded:
1. Be generous with analog and digital ground planes.
Mirror the ground plane with the supply planes. Use
a 5 mil power / ground plane separation if a four layer
board can be used.
2. Keep high frequency decoupling capacitors very
close to the A/D pins and minimize the loop area in-
cluded so less flux will induce less noise. Use de-
coupling capacitors in the same locations as on the
XRD8794AB.
3. Coupling between logic signals and analog circuitry
can easily change a 12-bit system into an 8-bit sys-
tem or worse. Completely separate them. Watch for
coupling opportunities from other sources not im-
mediately associated with the A/D. Don’t use switch-
ing power supplies in adjacent locations for exam-
ple.
4. Slow down the rising and falling edge of the input
CLOCK signal to minimize clock energy feed-
through.
5. Use support devices equivalent to those used on the
evaluation board. Use the application board to verify
these devices up front, i.e. use very linear passive
components in the signal path.
6. Select a driving op amp whose noise, speed, and lin-
earity fits the application.
7. Decoupling capacitors on pins R1, R2 and R3 do not
improve the ADC’s performance.
Rev. 1.00
12
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