XRD9825ACU View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRD9825ACU' PDF : 33 Pages View PDF
XRD9825
CCD
Channel N
ADCCLK
CLAMP
DB [5:0]
[11:6]
AREA, LINEAR or B/W CCD -- AC Coupled
(CLAMP Enabled)
Pixel N-1
Pixel N
Pixel N+1
tckpd
tap
tap
tckhw tcklw
tclpw
tdv
tdv
N-8 N-8 N-7 N-7 N-6
N-6
MSB LSB MSB LSB MSB LSB
Note: There is an 8 clock latency at the output.
Figure 15. Timing Diagram for Figure 14
Triple Channel CCD Application
Figure 6 is a block diagram for pixel-by-pixel applica-
tions with triple channel CCDs. During the optically
shielded section of a pixel, CLAMP must go high to
store the black reference on each capacitor to the input.
The gain and offset is automatically rotated to adjust for
each channel input. The MSBs (8 upper bits) are
available on the output bus on the falling edge of
ADCCLK. The LSBs (8 lower bits) are available on the
rising edge of ADCCLK.
Rev. 1.00
21
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