XRT71D00 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT71D00' PDF : 26 Pages View PDF
XRT71D00
E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
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FIGURE 6. ILLUSTRATION OF THE XRT71D00 (CONFIGURED TO OPERATE IN THE “HOST” MODE)
ICT
RClk
RPOS
RNEG
Timing Control Block /
Phase locked Loop
Jittery Clock
Smoothed
Clock
Write Clock
Read Clock
16/32 Bit FIFO
MClk
RRClk
RRPOS
RRNEG
FL
HOST/HW
Reset
Microprocessor Serial
Interface
CS SDI SDO SClk
The XRT71D00 DS3/E3/STS-1 Jitter Attenuator IC
consists of the following functional blocks:
• Jitter Attenuator Phase Locked Loop(PLL)
• Timing Control
• 2-Channel 16/32 Bit FIFO.
• Microprocessor Serial Interface
1.0 THE JITTER ATTENUATOR PLL
The Jitter Attenuator PLL is a narrow-band PLL that
accepts a “jittery” clock signal via the RCLK input pin.
The Jitter Attenuator PLL locks onto the RCLK input
signal and synthesizes a “same-rate” signal. As the
Jitter Attenuator PLL synthesizes this signal, it elimi-
nates much of the jitter that exists within the RCLK in-
put signal. The resulting smoothed clock signal is
then output via the “RRCLK” output signal.
1.1 THE JITTER TRANSFER CHARACTERISTICS OF THE
JITTER ATTENUATOR PLL
The Jitter Transfer Characteristics of the XRT71D00
device is ultimately dictated by the Jitter Transfer
Characteristics of the Jitter Attenuator PLL. The Jitter
Transfer Characteristics of the Jitter Attenuator PLL is
dictated by the following variables.
1. The operating mode/data rate of the XRT71D00
device.
2. The setting of the BWS (Bandwidth Select) input
pin or bit-field.
1.2 DEFINITION OF JITTER
One of the most important and least understood mea-
sures of clock performance is jitter. The International
Telecommunication Union defines jitter as “short term
variations of the significant instants of a digita signal
from their ideal positions in time”. Jitter can occur due
to any of the following:
1) Imperfect timing recovery circuit in the system
2) Cross-talk noise
3) Inter-symbol interference/Signal Distortion
1.3 JITTER TRANSFER CHARACTERISTICS
The primary purpose of jitter transfer requirements is
to prevent performance degradations by limiting the
accummulation of jitter through the system such that
it does not exceed the network interface jitter require-
ments. Thus, it is more important that a system meet
the jitter transfer criteria for relatively high input jitter
amplitudes. The jitter transferred through the system
must be under the jitter mask for any input jitter ampli-
tude within the range as shown in Figure 7
13
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