XRT71D00 View Datasheet(PDF) - Exar Corporation
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MFG CO.
'XRT71D00' PDF : 26 Pages View PDF
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XRT71D00
E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
The value of “A6” is a “don’t care”.
Once these first 8 bits have been written into the Seri-
al Interface, the subsequent action depends upon
whether the current operation is a “Read” or “Write”
operation.
3.2 READ OPERATION
Once the last address bit (A4) has been clocked into
the SDI input, the “Read” operation will proceed
through an idle period, lasting three SClk periods. On
the falling edge of SClk Cycle #8 (see Figure 11) the
serial data output signal (SDO) becomes active. At
this point the user can begin reading the data con-
tents of the addressed Command Register (at Ad-
dress [A4, A3, A2, A1, A0]) via the SDO output pin.
The Serial Interface will output this eight bit data word
(D0 through D7) in ascending order (with the LSB
first), on the falling edges of the SClk . The data (on
the SDO output pin) is stable for reading on the very
next rising edge of the SClk .
3.3 WRITE OPERATION
Once the last address bit (A4) has been clocked into
the SDI input, the “Write” operation will proceed
through an idle period, lasting three SClk periods. Pri-
or to the rising edge of SClk Cycle #9 , the eight bit
data word is applied to SDI input. Data on SDI is
latched on the rising edge of SClk.
FIGURE 11. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
CS
SClk
SDI
SDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
R/W A0 A1 A2 A3 A4 0 A6 D0 D1 D2 D3 D4 D5 D6 D7
High Z
High Z
D0 D1 D2 D3 D4 D5 D6 D7
NOTES:
1. A5 is always “0”.
2. R/W = “1” for “Read” Operations
3. R/W = “0” for “Write” Operations
4. Denotes a “don’t care” value (shaded areas)
3.4 SIMPLIFIED INTERFACE OPTION
The user can simplify the design of the circuitry con-
necting to the Microprocessor Serial Interface by ty-
ing both the SDO and SDI pins together, and reading
data from and/or writing data to this “combined” sig-
nal. This simplification is possible because only one
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