XRT72L13 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT72L13' PDF : 370 Pages View PDF
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PRELIMINARY
PIN DESCRIPTIONS
PIN #
NAME
203
RxOHInd/
RxPLClkEnb
204
RxClk
205
RxFrame
206
RxInClk
207
RxDS1Data_27
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
TYPE
O
O
O
I
O
DESCRIPTION
Receive Overhead Bit Indicator:
This output pin pulses "high" whenever an "overhead" bit is being out-
put via the "RxSer" output pin, by the "Receive Payload Data Output
Interface" block.
The purpose of this output pin is to alert the "Receive Terminal Equip-
ment" that an overhead bit is being output via the "RxSer" output pin,
and that this data should be ignored.
Receive Clock Output Signal for Serial and Nibble/Parallel Data
Interface:
The exact behavior of this signal depends upon whether the
XRT72L13 is operating in the “Clear-Channel-Framing/Serial” or
“Clear-Channel-Framing/Nibble-Parallel” Modes.
Clear-Channel Framing - Serial Mode Operation:
In the "serial" mode, this signal is a 44.736MHz clock output signal.
The Receive Payload Data Output Interface will update the data via
the RxSer output pin, upon the rising edge of this clock signal.
The user is advised to design (or configure) the Terminal Equipment
to sample the data on the "RxSer" pin, upon the falling edge of this
clock signal.
Clear-Channel Framing - Nibble-Parallel Mode Operation
In this Nibble-Parallel Mode, the XRT72L13 will derive this clock sig-
nal, from the RxLineClk signal. The XRT72L13 will pulse this clock
signal 1176 times for each "inbound" DS3 frame. The Receive Pay-
load Data Output Interface will update the data, on the "RxNib[3:0]"
output pins upon the falling edge of this clock signal.
The user is advised to design (or configure) the Terminal Equipment
to sample the data on the "RxNib[3:0] output pins, upon the rising
edge of this clock signal
Receive Boundary of DS3 Frame Output Indicator:
The funtion of this output pin depends upon whether the XRT72L13
Framer IC is operating in the “Clear-Channel-Framing/Serial” or
“Clear-Channel-Framing/Nibble-Parallel” Modes.
Clear-Channel Framing - Serial Mode Operation
The Receive Section of the XRT72L13 will pulse this output pin “high”
(for one bit-period) when the “Receive Payload Data Output Interface”
block is driving the very first bit of a given given DS3 frame, onto the
“RxSer” output pin.
Clear-Channel Framing -Nibble-Parallel Operation
The Receive Section of the XRT72L13 will pulse this output pin “high”
(for one nibble-period), when the “Receive Payload Data Output Inter-
face” block is driving the very first nibble of a given DS3 frame, onto
the “RxNib[3:0] output pins.
Receive Input Clock:
Receive DS1 Data Output - Channel 27:
This pin outputs a DS1 signal from the M12 multiplexer. Each bit,
within the DS1 data stream is output upon the rising edge of
RxDS1Clk_27.
NOTES:
1. This output pin is inactive if the corresponding M12 DEMUX is
de-multiplexing an ITU-T G.747 data stream.
2. This pin will output the contents of DS2 channel # 7, if M12
MUX # 7 is bypassed.
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