áç
PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
AC ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: TA = 25(C, VCC = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP.
t78 A8 - A0 Setup Time to falling edge of ALE_AS
5
t79 A8 - A0 risinfg edge of RD_DS to rising edge of
0
RDY_DTCK delay
t80 Rising edge of RDY_DTCK to tri-state of D[7:0]
0
Microprocessor Interface - Motorola Write Operations (See Figure 21)
t78 A8 -A0 Set-up time to falling edge of ALE_AS
5
t81 D[7:0] Set-up time to falling edge of RD_DS
10
t82 Rising edge of RD_DS to rising edge of RDY_DTCK 0
Reset Pulse Width - Both Motorola and Intel Operations (See Figure 24)
t90 Reset pulse width
200
MAX.
UNITS
ns
ns
ns
ns
ns
ns
CONDITIONS
FIGURE 2. TIMING DIAGRAM FOR TRANSMIT PAYLOAD INPUT INTERFACE, WHEN THE XRT72L13 IS OPERATING IN
BOTH THE DS3 AND LOOP-TIMING MODES
XRT72L13 Transmit Payload Data I/F Signals
t3
RxOutClk
t2
t1
TxSer
TxFrame
TxOH_Ind
Payload[4702] Payload[4703]
X-Bit
Payload[0]
t4
DS3 Frame Number N
DS3 Frame Number N + 1
43