XRT72L13 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT72L13' PDF : 370 Pages View PDF
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PRELIMINARY
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC XRT72L13
REV. 1.0.6
This “Read-Only” bit-field indicates whether or not an
“M13 Multiplexer” related interrupt has been request-
ed and is awaiting service.
If this bit-field is set to “0”, then there are no “M13
Multiplexer” related interrupts awaiting service. Con-
versely, if this bit-field is set to “1”, then there is at
least one “M13 Multiplexer” related interrupt, awaiting
service.
Bit 1 - Tx DS3 Interrupt Status
This “Read-Only” bit-field indicates whether or not a
“Transmit DS3 Framer” related interrupt has been re-
quested and is awaiting service.
If this bit-field is set to “0”, then there are no “Transmit
DS3 Framer” related interrupts awaiting service.
Conversely, if this bit-field is set to “1”, then there is at
least one “Transmit DS3 Framer” related interrupt,
awaiting service.
Bit 0 - One Second Interrupt Status
This “Reset-upon-Read” bit-field indicates whether or
not a “One Second” interrupt has been requested and
is awaiting service.
If this bit-field is set to “0”, then the “One Second” in-
terrupt is not awaiting service. Conversely, if this bit-
field is set to “1”, then the “One Second” interrupt is
awaiting service.
NOTE: This bit-field will be cleared immediately after the
Microprocessor/Microcontroller has read this register.
2.3.2.8 RxFIFO Control Register
RXFIFO CONTROL REGISTER (ADDRESS = 0X06)
BIT 7
Not Used
R/O
0
BIT 6
Not Used
R/O
0
BIT 5
Not Used
R/O
0
BIT 4
Not Used
R/O
0
BIT 3
Not Used
R/O
0
BIT 2
Not Used
R/O
0
BIT 1
RxFIFO32
R/W
0
BIT 0
RxFIFO
Enable
R/W
0
Bit 1 - RxFIFO32 - 32/64 Operating Depth Select
This “Read/Write” bit-field permits the user to config-
ure the operating depth of the “de-jitter” FIFO to be ei-
ther 32 or 64 bits.
Setting this bit-field to “0” configures the operating
depth of the “De-Jitter” FIFO to be 64 bits.
Setting this bit-field to “1” configures the operating
depth of the “De-Jitter” FIFO to be 32 bits.
NOTE: This bit-field is ignored if the “De-Jitter FIFO” is dis-
abled.
Bit 0 - RxFIF0 Enable
This “Read/Write” bit-field permits the user to enable
or disable the “De-Jitter” FIFO within the XRT72L13.
Setting this bit-field to “0” disables the “De-Jitter”
FIFO.
Setting this bit-field to “1” enables the “De-Jitter” FIFO
2.3.2.9 M23 Configuration Register
M23 CONFIGURATION REGISTER (ADDRESS = 0X07)
BIT 7
Not Used
R/O
0
BIT 6
Payload
HDLC
Controller
Enable
R/W
0
BIT 5
RxDS1Clk
Gapped
(CRC-32)
R/W
0
BIT 4
M13
Disable
R/W
0
BIT 3
M13
Loopback/
(Remote
Loopback)
R/W
0
BIT 2
Tributary
Polarity
R/W
0
BIT 1
M23
Loopback
Code[1]
R/W
0
BIT 0
M23
Loopback
Code[0]
R/W
0
Bit 6 - Payload HDLC Controller Enable
This bit-field along with “M13 Disable” (bit 4) pemits
the user to specify whether the XRT72L13 M13 de-
vice is to operate in either of the following modes.
• The “M13/Channelized” Mode
• The “DS3 Clear Channel Framer” Mode
• The “High Speed HDLC Controller” Mode.
The relationship between these two bit-fields and the
resulting operating operating mode of the XRT72L13
M13 device is tabulated below.
87
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