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PRELIMINARY
XRT72L58
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
PIN DESCRIPTION FOR THE XRT72L58
PIN #
A5
PIN NAME
RxNib1[7]/
RxHDLCDat1[7]
A6
TxOHInd[7]/
TxHDLCDat6[7]
A7
RxOHClk[7]/
RxHDLCClk[7]
A8
RxLOS[0]
TYPE
O
O
I
O
O
DESCRIPTION
Receive Nibble Output - 1:
The Framer will output "Received data (from the Remote Terminal) to the local
Terminal Equipment via this pin along with RxNib0, RxNib2 and RxNib3.
The data at this pin is updated on the rising edge of the RxClk output signal.
NOTE: This output pin is active only if the Nibble-Parallel Mode has been
selected.
Receive HDLC Data Output - 1:
This pin contains bit 1 RxHDLC data when the HDLC controller is turned on.
Transmit Overhead Data Indicator:
This output pin will pulse "high" one-bit period prior to the time that the Trans-
mit Section of the XRT72L58 will be processing an Overhead bit. The pur-
pose of this output pin is to warn the Terminal Equipment that, during the very
next bit-period, the XRT72L58 is going to be processing an "Overhead" bit
and will be ignoring any data that is applied to the "TxSer" input pin.
NOTE: For DS3 applications, this output pin is only active if the XRT72L58 is
operating in the "Serial" Mode. This output pin will be pulled "low" if the
Framer is operating in the "Nibble-Parallel" Mode.
Transmit HDLC Data Input - 6:
This pin accepts bit 6 TxHDLC data when the HDLC controller is turned on.
Receive Overhead Output Clock Signal:
The XRT72L58 will output the Overhead bits (within the incoming DS3 or E3
frames), via the "RxOH" output pin, upon the falling edge of this clock signal.
As a consequence, the "user's data link equipment" should use the rising
edge of this clock signal to sample the data on both the "RxOH" and "RxO-
HFrame" output pins.
NOTE: This clock signal is always active.
Receive HDLC Output Clock:
When the HDLC controller is on, RxHDLCDat is updated by the 72L58 on this
clock signal.
Receive Section - Loss of Signal Output Indicator:
This pin is asserted when the Receive Section encounters a string of 180
consecutive 0's (for DS3 operation) or 32 consecutive 0's (for E3 operation)
via the RxPOS and RxNEG pins.
This pin will be negated once the Receive Section has detected at least 60
pulses within 180 bit-periods (for DS3 operation); or the Receive Section has
detected a string of 32 consecutive bits, that does not contain a string of 4
consecutive "0s" (for E3 operation).
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