áç
XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
MICROPROCESSOR SERIAL INTERFACE TIMING (SEE FIGURE 9)
SYMBOL
PARAMETER
MIN.
t21 CS Low to Rising Edge of SCLK Setup Time
50
t22 CS High to Rising Edge of SCLK Hold Time
20
t23 SDI to Rising Edge of SCLK Setup Time
50
t24 SDI to Rising Edge of SCLK Hold Time
50
t25 SCLK “Low” Time
240
t26 SCLK “High” Time
240
t27 SCLK Period
500
t28 CS Low to Rising Edge of SCLK Hold Time
50
t29 CS Inactive Time
250
t30 Falling Edge of SCLK to SDO Valid Time
t31 Falling Edge of SCLK to SDO Invalid Time
t32 Falling Edge of SCLK or Rising Edge of CS to High Z
t33 Rise/Fall time of SDO Output
TYP.
MAX.
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
ns
100
ns
100
ns
40
ns
FIGURE 9. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
CS
SCLK
SDI
t21
t22
t23
t24
R/W
t27
t25
t26
A0
A1
t29
t28
CS
SCLK
t30
t31
SDO Hi-Z
D0
D1
Hi-Z
SDI
t33
D2
17
t32
D7