XRT7302 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.0
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FIGURE 3. TIMING DIAGRAM OF THE RECEIVE TERMINAL OUTPUT INTERFACE
tCO
RPOS
RNEG
RxCLK
FIGURE 4. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
CS
SClk
SDI
SDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
R/W A0 A1 A2 A3 A4 0 A6 D0 D1 D2 D3 D4 D5 D6 D7
High Z
High Z
D0 D1 D2 D3 D4 0 0 0
NOTES:
1. A4 and A5 are always "0".
2. R/W = "1" for "Read" Operations
3. R/W = "0" for "Write" Operations
4. A shaded pulse, denotes a “don’t care” value.
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