XRT7302IV View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT7302IV' PDF : 62 Pages View PDF
XRT7302 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.1.6
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PRELIMINARY
TABLE 7: ADDRESSES AND BIT FORMATS OF XRT7302 COMMAND REGISTERS
REGISTER BIT-FORMAT
ADDRESS
COMMAND
REGISTER
TYPE
D4
D3
D2
D1
CHANNEL 0
0x00
CR0-0
RO
RLOL0
RLOS0
ALOS0
DLOS0
0x01
CR1-0
R/W
TxOFF0
TAOS0
TxClkINV0
TxLEV0
0x02
CR2-0
R/W
Reserved ENDECDIS0 ALOSDIS0 DLOSDIS0
0x03
CR3-0
R/W
SR/DR_0
LOSMUT0
RxOFF0 RxClk0INV
0x04
CR4-0
R/W
Reserved STS-1/DS3_Ch0 E3_CH0
LLB0
0x05
CR5-0
R/W
Reserved
Reserved
Reserved Reserved
0x06
CR6-0
R/W
Reserved
Reserved
Reserved Reserved
0x07
CR7-0
R/W
Reserved
Reserved
CHANNEL 1
Reserved Reserved
0x08
CR0-1
RO
RLOL1
RLOS1
ALOS1
DLOS1
0x09
CR1-1
R/W
TxOFF1
TAOS1
TxClkINV1
TxLEV1
0x0A
CR2-1
R/W
Reserved ENDECDIS1 ALOSDIS1 DLOSDIS1
0x0B
CR3-1
R/W
SR/DR_1
LOSMUT1
RxOFF1 RxClk1INV
0x0C
CR4-1
R/W
Reserved STS-1/DS3_Ch1 E3_CH1
LLB1
0x0D
CR5-1
R/W
Reserved
Reserved
Reserved Reserved
0x0E
CR6-1
R/W
Reserved
Reserved
Reserved Reserved
0x0F
CR7-1
R/W
Reserved
Reserved
Reserved Reserved
D0
DMO0
TxBIN0
REQEN0
Reserved
RLB0
Reserved
Reserved
Reserved
DMO1
TxBIN1
REQEN1
Reserved
RLB1
Reserved
Reserved
Reserved
Address
The register addresses are presented in the Hexa-
decimal format.
Type:
The Command Registers are either Read-Only (RO)
or Read/Write (R/W) registers. Each channel of the
XRT7302 has eight command registers, CR0-(n)
through CR7-(n) where (n) = 0 or 1. The associated
addresses for each channel is presented in Table 7.
NOTE: The default value for each of the bit-fields in these
registers is "0".
5.2 DESCRIPTION OF BIT-FIELDS FOR EACH COM-
MAND REGISTER
5.2.1 Command Register - CR0-(n)
The bit-format and default values for Command Reg-
ister CR0-(n) are listed below followed by the function
of these bit-fields.
COMMAND REGISTER CR0-(N)
D4
RLOL
1
D3
RLOS
1
D2
ALOS
1
D1
DLOS
1
D0
DMO
1
Bit D4 - RLOL(n) (Receive Loss of Lock Status -
Channel(n))
This Read-Only bit-field reflects the lock status of the
Channel(n) Clock Recovery Phase-Locked-Loop in
the XRT7302.
This bit-field is set to “0" if the Clock Recovery PLL is
in lock with the incoming line signal. This bit-field is
50
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