XRT73L03 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT73L03' PDF : 62 Pages View PDF
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PRELIMINARY
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT XRT73L03
REV. P1.0.13
FIGURE 8. FUNCTIONAL BLOCK DIAGRAM OF THE XRT73L03
E3_Ch(n) STS-1/DS3_Ch(n) Host/(HW) RLOL(n) EXClk(n)
RxOFF
RxClkINV
RTIP(n)
RRing(n)
REQEN(n)
LOSTHR(n)
SDI
SDO
SClk
CS
REGR
TTIP(n)
TRing(n)
MTIP(n)
MRing(n)
DMO(n)
AGC/
Equalizer
Peak
Detector
Slicer
Clock
Recovery
LOS Detector
Serial
Processor
Interface
Loop MUX
Data
Recovery
Invert
HDB3/
B3ZS
Decoder
Device
Monitor
Pulse
Shaping
Tx
Control
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
Channel 1 - (n) = 1
Channel 2 - (n) = 2
Channel 3 - (n) = 3
RxClk(n)
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
RLOS(n)
LLB(n)
RLB(n)
TAOS(n)
TPData(n)
TNData(n)
TxClk(n)
TxLEV(n)
TxOFF(n)
Notes: 1. (n) = 1, 2 or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
1.0 SELECTING THE DATA RATE
Each channel in the XRT73L03 can be configured to
support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or
SONET STS-1 (51.84 Mbps) rates and to operate in a
mode/data rate that is independent of the other chan-
nels.
Two methods are available to select the data rate for
each channel of the XRT73L03.
1.1 CONFIGURING CHANNEL(N)
Refer to Table 2 to determine the appropriate
Address for each Command Register of each chan-
nel in the XRT73L03. The Command Register
description refers to CR(m)-(n), where (m) = 0 to 7
and (n) refers to a particular channel of the
XRT73L03.
TABLE 2: ADDRESSES AND BIT FORMATS OF XRT73L03 COMMAND REGISTERS
REGISTER BIT-FORMAT
ADDRESS
COMMAND
REGISTER
TYPE
D4
D3
D2
D1
D0
CHANNEL1
0x00
CR0-1
RO
RLOL1
RLOS1
ALOS1
DLOS1
DMO1
0x01
CR1-1
R/W
TxOFF1
TAOS1
TxClkINV1 TxLEV1
TxBIN1
0x02
CR2-1
R/W
Reserved ENDECDIS1 ALOSDIS1 DLOSDIS1 REQEN1
0x03
CR3-1
R/W
SR/(DR)_1 LOSMUT1
RxOFF1 RxClk1INV Reserved
0x04
CR4-1
R/W
Reserved STS-1/DS3_Ch1 E3_Ch1
LLB1
RLB1
24
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