XRT73L03 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT73L03' PDF : 62 Pages View PDF
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PRELIMINARY
XRT73L03
AUGUST 2000
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.13
GENERAL DESCRIPTION
The XRT73L03 is a 3-Channel, E3/DS3/STS-1 Line
Interface Unit designed for E3, DS3 or SONET STS-1
applications and consists of three independent line
transmitters and receivers integrated on a single chip.
Each channel of the XRT73L03 can be configured to
support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or
the SONET STS-1 (51.84 Mbps) rates. Each channel
can be configured to operate in a mode/data rate that
is independent of the other channels.
In the transmit direction, each channel in the
XRT73L03 encodes input data to either B3ZS or
HDB3 format and converts the data into the appropri-
ate pulse shapes for transmission over coaxial cable
via a 1:1 transformer.
In the receive direction, the XRT73L03 can perform
Equalization on incoming signals, perform Clock Re-
covery, decode data from either B3ZS or HDB3 for-
mat, convert the receive data into TTL/CMOS format,
check for LOS or LOL conditions and detect and de-
clare the occurrence of Line Code Violations.
APPLICATIONS
• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
• Multiplexers
• ATM Switches
FEATURES
• Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
• Full Loop-Back Capability
• Transmit and Receive Power Down Modes
• Full Redundancy Support
• Contains a 4-Wire Microprocessor Serial Interface
• Uses Minimum External components
• Single +3.3V Power Supply
• 5V tolerant I/O
• -40°C to +85°C Operating Temperature Range
• Available in a Thermally Enhanced 120 pin TQFP
package
FIGURE 1. XRT73L03 BLOCK DIAGRAM
E3_Ch(n) STS-1/DS3_Ch(n) Host/(HW) RLOL(n) EXClk(n)
RxOFF
RxClkINV
RTIP(n)
RRing(n)
REQEN(n)
LOSTHR(n)
SDI
SDO
SClk
CS
REGR
TTIP(n)
TRing(n)
MTIP(n)
MRing(n)
DMO(n)
AGC/
Equalizer
Peak
Detector
Slicer
Clock
Recovery
LOS Detector
Serial
Processor
Interface
Loop MUX
Data
Recovery
Invert
HDB3/
B3ZS
Decoder
Device
Monitor
Pulse
Shaping
Tx
Control
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
Channel 1 - (n) = 1
Channel 2 - (n) = 2
Channel 3 - (n) = 3
RxClk(n)
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
RLOS(n)
LLB(n)
RLB(n)
TAOS(n)
TPData(n)
TNData(n)
TxClk(n)
TxLEV(n)
TxOFF(n)
Notes: 1. (n) = 1, 2 or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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