XRT73L04A
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.3
In HOST Mode Operation, the TxOFF input pins can
be used to turn on or turn off the Transmit Output
Drivers within all Channels concurrently. The intent
behind this feature is to permit a system designed for
redundancy to quickly switch out a defective line card
and switch-in the back-up line card.
FIGURE 13. FUNCTIONAL BLOCK DIAGRAM OF THE XRT73L04A
E3_(n) STS-1/DS3_(n)
Host/(HW) RLOL_(n) EXClk_(n) RxOFF
RxClkINV
RTIP_(n)
RRing_(n)
AGC/
Equalizer
Slicer
Clock
Recovery
Invert
REQEN_(n)
LOSTHR
SDI
SDO
SClk
CS/(SR/DR)
REGR
Peak
Detector
LOS Detector
Serial
Processor
Interface
Loop MUX
Data
Recovery
HDB3/
B3ZS
Decoder
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
MTIP_(n)
MRing_(n)
DMO_(n)
Device
Monitor
Tx
Control
Channel 0
Channel 1
Channel 2
Channel 3
Notes: 1. (n) = 0, 1, 2 , or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in
Hardware Mode.
RxClk_(n)
RPOS_(n)
RNEG_(n)/
(LCV_(n))
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF
1.0 SELECTING THE DATA RATE
Each channel within the XRT73L04A can be config-
ured to support the E3 (34.368 Mbps), DS3 (44.736
Mbps) or the SONET STS-1 (51.84 Mbps) rates. Fur-
ther, each channel can be configured to operate in a
mode/data rate that is independent of the other chan-
nels.
Two methods are available to select the data rate for
each channel of the XRT73L04A.
1.1 CONFIGURING CHANNEL(n)
For the following disscussion the reader should refer
toTable 2 to determine the appropriate Address for
each command register of each channel in the
XRT73L04A. The command register description re-
fers to CR(x)-(n), where (x) = 0 to 7 and (n) refers to a
particular channel of the XRT73L04A.
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