XRT73L06 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT73L06' PDF : 63 Pages View PDF
XRT73L06
REV. 1.0.2
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS
(HEX)
TYPE
REGISTER
NAME
BIT#
D0
D1
D2
D3
SYMBOL
DESCRIPTION
Reserved This bit is Reserved.
Reserved This bit is Reserved.
Reserved This bit is Reserved.
Reserved This bit is Reserved.
DEFAULT
VALUE
0
0
0
0
D4 DFLCK_n Set this bit to “1” to disable fast locking of the PLL.
0
0x07 (Ch 0) R/W Jitter
This helps to reduce the time for the PLL to lock to
0x17 (Ch 1)
Attenuator
incoming frequency when the Jitter Attenuator
0x27 (Ch 2)
switches to narrow band.
0x37 (ch 3)
0x47 (ch 4)
D7-D5
Reserved
0x57 (ch 5)
55
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