XRT75L00D View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT75L00D' PDF : 92 Pages View PDF
XRT75L00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.2
JITTER ATTENUATOR INTERFACE
PIN #
6
SIGNAL NAME
JA0
TYPE
I
DESCRIPTION
Disable Jitter Attenuator/FIFO Size Select::
In Hardware Mode, this pin along with JA1 pin provides the following functions
in the table below.
7
JA1
8
JA Tx/Rx
JA0
JA1
Operation
0
0
16 bit FIFO
0
1
32 bit FIFO
1
0
128 bit FIFO
1
1
Disable Jitter
Attenuator
NOTE: This pin is internally pulled down.
I
Disable Jitter Attenuator/FIFO Size Select:
In Hardware Mode, this pin along with JA0 pin provides the functions in the
table above.
NOTE: This pin is internally pulled down.
I
Jitter Attenuator Select:
In Hardware Mode setting this pin “High” selects the Jitter Attenuator in the
Transmit path and setting “Low” selects in Receive path.
NOTE: This pin is internally pulled down.
13
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