XRT75L02 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT75L02' PDF : 50 Pages View PDF
xr
REV. 1.0.3
XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
TABLE 19: REGISTER MAP DESCRIPTION - CHANNEL 0
ADDRESS
(HEX)
REGISTER
TYPE
BIT#
NAME
SYMBOL
DESCRIPTION
DEFAULT
VALUE
D0 DMOIE_n Writing a “1” to this bit enables an interrupt when the
0
no transmission detected on channel output.
D1 RLOSIE_n Writing a “1” to this bit enables an interrupt when
0
Receive Los of Signal is detected.
D2 RLOLIE_n Writing a “1” to this bit enables an interrupt when
0
Receive Loss of Lock condition is detected
0x01 (ch 0) R/W Interrupt
D3 FLIE_n Writing a “1” to this bit enables the interrupt when
0
0x09 (ch 1)
Enable
(source
the FIFO Limit of the Jitter Attenuator is within 2 bits
of overflow/underflow condition.
level)
NOTE: This bit field is ignored when the Jitter
Attenuator is disabled.
D7-D4
Reserved
D0 DMOIS_n This bit is set every time a DMO status change has
0
occurred since the last cleared interrupt.This bit is
cleared when the register bit is read.
D1 RLOSIS_n This bit is set every time a RLOS status change has
0
occurred since the last cleared interrupt. This bit is
cleared when the register bit is read.
D2 RLOLIS_n This bit is set every time a RLOL status change has
0
0x02 (ch 0) Reset Interrupt
occurred since the last cleared interrupt. This bit is
0x0A (ch 1) on Status
cleared when the register bit is read.
Read (source
level)
D3 FLIS_n This bit is set every time a FIFO Limit status change
0
has occurred since the last cleared interrupt. This bit
is cleared when the register bit is read.
D7-D4
Reserved
D0 DMO_n This bit is set every time the MTIP_0/MRing_0 input
0
pins have not detected any bipolar pulses for 128
consecutive bit periods.
D1 RLOS_n This bit is set every time the receiver declares an
0
LOS condition.
D2 RLOL_n This bit is set every time when the receiver declares
0
a Loss of Lock condition.
D3
FL_n This bit is set every time the FIFO in the Jitter Atten-
0
uator is within 2 bit of underflow/overflow condition.
D4 ALOS_n This bit is set every time the receiver declares Ana-
0
0x03 (ch 0) Read Alarm Sta-
log LOS condition.
0x0B (ch 1) Only tus
D5 DLOS_n This bit is set every time the receiver declares Digi-
0
tal LOS condition.
D6 PRBSLS_n This bit is set every time the PRBS detector is not in
0
sync.
D7
Reserved
38
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