XRT75L03 View Datasheet(PDF) - Exar Corporation

Part Name

Description

MFG CO.

XRT75L03

THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

Exar Corporation 

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XRT75L03

REV. 1.0.4

THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

TABLE 15: XRT75L03 REGISTER MAP - QUICK LOOK

ADDRESS

LOCATION

REGISTER NAME

0x0C

Transmit Control

Register - Ch 0

0x0D

Receive Control

Register - Ch 0

0x0E

0x0F

Channel Control

Register - Ch 0

Jitter Attenuator

Control Register -

Ch 0

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Reserved

Internal

Transmit

Drive

Monitoring

Insert

PRBS

Error

Unused

TAOS TxCLK INV TxLEV

Reserved

DisableD- DisableA-

LOS LOS Detec-

Detector

tor

RxCLK

INV

LOSMUTEn-

able

Receive

Monitor

Mode

Enable

Receive

Equalizer

Enable

Reserved

PRBS

RLB

Enable

LLB

E3 Mode STS-1/DS3 SR/DR

Mode

Mode

Reserved

JA

RESET

JA1

(JA Mode

Select Bit 1)

JA in

TxPath

JA0

(JA Mode

Select 0)

0x10

Reserved

CHANNEL 2 REGISTERS

Reserved Reserved Reserved

Reserved

Reserved

Reserved

0x11

Source Level

Interrupt Enable

Register - Ch 0

Reserved

Change of

FL Alarm

Condition

Interrupt

Enable

Change of

RLOL

Condition

Interrupt

Enable

Change of

RLOS

Defect

Condition

Interrupt

Enable

Change of

DMO

Condition

Interrupt

Enable

0x12

Source Level

Interrupt Status

Register - Ch 0

Reserved

Change of

FL Alarm

Condition

Interrupt

Status

Change of

RLOL

Condition

Interrupt

Status

Change of

RLOS

Condition

Interrupt

Status

Change of

DMO

Condition

Interrupt

Status

0x13

Alarm Status

Register - Ch 0

Reserved Loss of

PRBS

Pattern Sync

DLOS

Defect

Declared

ALOS

Defect

Declared

FL Alarm

Declared

RLOL

Condition

Declared

RLOS

Defect

Condition

DMO

Condition

Status

0x14

Transmit Control

Register - Ch 0

Reserved

Internal

Transmit

Drive

Monitoring

Insert

PRBS

Error

Unused

TAOS TxCLK INV TxLEV

0x15

Receive Control

Register - Ch 0

Reserved

DisableD- DisableA-

LOS LOS Detec-

Detector

tor

RxCLK

INV

LOSMUTEn-

able

Receive

Monitor

Mode

Enable

Receive

Equalizer

Enable

0x16

0x17

Channel Control

Register - Ch 0

Jitter Attenuator

Control Register -

Ch 0

Reserved

PRBS

Enable

Reserved

RLB

LLB

E3 Mode STS-1/DS3 SR/DR

Mode

Mode

JA

RESET

JA1

(JA Mode

Select Bit 1)

JA in

TxPath

JA0

(JA Mode

Select 0)

0x19 -

0x1F

Reserved

Reserved

0x20

Block Level

Interrupt Enable

Register - Ch 32

55

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