XRT75L03 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT75L03' PDF : 92 Pages View PDF
XRT75L03
REV. 1.0.4
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 30: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07
Channel 1 Address Location = 0x0F
Channel 2 Address Location = 0x17
BIT 7
BIT 6
BIT 5
Unused
BIT 4
BIT 3
JA RESET
Ch_n
BIT 2
JA1 Ch_n
BIT 1
JA in Tx Path
Ch_n
BIT 0
JA0 Ch_n
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-4
3
Unused
JA RESET Ch_n
2
JA1 Ch_n
TYPE
R/O
R/W
R/W
DEFAULT
VALUE
DESCRIPTION
0
0
Jitter Attenuator RESET - Channel_n:
Writing a "0 to 1" transition within this bit-field will configure
the Jitter Attenuator (within Channel_n) to execute a
RESET operation.
Whenever the user executes a RESET operation, then all
of the following will occur.
• The READ and WRITE pointers (within the Jitter
Attenuator FIFO) will be reset to their default values.
• The contents of the Jitter Attenuator FIFO will be
flushed.
NOTE: The user must follow up any "0 to 1" transition with
the appropriate write operate to set this bit-field
back to "0", in order to resume normal operation
with the Jitter Attenuator.
0
Jitter Attenuator Configuration Select Input - Bit 1:
This READ/WRITE bit-field, along with Bit 0 (JA0 Ch_n) is
used to do any of the following.
• To enable or disable the Jitter Attenuator corresponding
to Channel_n.
• To select the FIFO Depth for the Jitter Attenuator within
Channel_n.
The relationship between the settings of these two bit-
fields and the Enable/Disable States, and FIFO Depths is
presented below.
JA0 JA1
0
0
0
1
1
0
1
1
Jitter Attenuator Mode
FIFO Depth = 16 bits
FIFO Depth = 32 bits
Disabled
Disabled
83
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