XRT75L04 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT75L04' PDF : 57 Pages View PDF
REV. 1.0.4
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
SERIAL MICROPROCESSOR INTERFACE
87
SDI
RxON
I
Serial Data Input:
Data is serially input through this pin.
The input data is sampled on the rising edge of the SClk pin (pin 88).
NOTES:
1. This pin is internally pulled down
2. If configured in Hardware Mode, this pin functions as RxON.
85
SDO
RxMON
I/O Serial Data Output:
This pin serially outputs the contents of the specified Command Register during
Read Operations. The data is updated on the falling edge of the SClk and this
pin is tri-stated upon completion of data transfer.
NOTE: If configured in Hardware Mode, this pin functions as RxMON.
84
INT
LOSMUT
I/O INTERRUPT Output:
This pin functions as Interrupt Output for Serial Interface. A transition to “Low”
indicates that an interrupt has been generated by the Serial Interface. The inter-
rupt function can be disabled by setting the interrupt enable bit to “0” in the
Channel Control Register.
NOTES:
1. In Hardware mode, this pin functions as LOSMUT.
2. This pin will remain asserted “Low” until the interrupt is serviced.
133
RESET
I Register Reset:
Setting this input pin "Low" causes the XRT75L04 to reset the contents of the
Command Registers to their default settings and default operating configuration
NOTE: This pin is internally pulled up.
JITTER ATTENUATOR INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
154
JA1
I
Jitter Attenuator Select 1:
In Hardware Mode, this pin along with the pin JA0 configures the Jitter Attenua-
tor as shown in the table.
JA0
JA1
0
0
0
1
1
0
1
1
NOTE: This pin is internally pulled down.
Mode
16 bit FIFO
32 bit FIFO
Disable Jitter
Attenuator
Disable Jitter
Attenuator
13
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