XRT75L04 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT75L04' PDF : 57 Pages View PDF
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TRANSMIT INTERFACE
REV. 1.0.4
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
88
TxClkINV/
SClk
I
Hardware Mode: Transmit Clock Invert
Host Mode: Serial Clock Input:
Function of this pin depends on whether the XRT75L04 is configured to operate
in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” configures all three Transmitters
to sample the TPOS_n and TNEG_n data on the rising edge of the TxCLK_n .
NOTES:
1. If the XRT75L04 is configured in HOST mode, this pin functions as
SClk input pin (please refer to the pin description for Microprocessor
interface).
152
TxMON
I
Transmitter Monitor:
When this pin is pulled “High”, MTIP and MRING are connected internally to
TTIP and TRING and allows self monitoring of the transmitter.
51
TAOS_0
48
TAOS_1
170
TAOS_2
173
TAOS_3
I Transmit All Ones Select - Channel 0:
Transmit All Ones Select - Channel 1:
Transmit All Ones Select - Channel 2:
Transmit All Ones Select - Channel 3:
A “High" on this pin causes the Transmitter Section of Channel_n to generate
and transmit a continuous AMI all “1’s” pattern onto the line. The frequency of
this “1’s” pattern is determined by TxClk_n.
NOTES:
1. This input pin is ignored if the XRT75L04 is operating in the HOST
Mode and should be tied to GND.
2. Analog Loopback and Remote Loopback have priority over request.
3. This pin is internally pulled down.
6
Share Link: 
