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XRT79L71 View Datasheet(PDF) - Exar Corporation

Part Name
Description
MFG CO.
'XRT79L71' PDF : 109 Pages View PDF
XRT79L71
PRELIMINARY
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
5.3.1.10 RECEIVE DS3/E3 LIU BLOCK INTERRUPTS ....................................................................................................... 371
5.3.2 THE RECEIVE E3 FRAMER BLOCK ....................................................................................................................... 371
FIGURE 173. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS
BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.751 CLEAR-CHANNEL FRAMER MODE (WITH THE "RECEIVE DS3/E3 FRAM-
ER" BLOCK HIGHLIGHTED).............................................................................................................................................. 372
5.3.2.1 THE FRAME-ACQUISITION MODES .............................................................................................................. 373
FIGURE 174. THE RECEIVE E3 FRAMER BLOCK'S FRAME ACQUISITION/MAINTENANCE ALGORITHM - E3, ITU-T G.751 APPLICATIONS373
FIGURE 175. THE STATE MACHINE DIAGRAM FOR THE RECEIVE E3 FRAMER BLOCK'S "FRAME ACQUISITION/MAINTENANCE" ALGORITHM
(WITH THE "FAS PATTERN SEARCH STATE" SHADED) .................................................................................................... 374
FIGURE 176. THE STATE MACHINE DIAGRAM FOR THE RECEIVE E3 FRAMER BLOCK'S "FRAME ACQUISITION/MAINTENANCE" ALGORITHM
(WITH THE "FAS PATTERN VERIFICATION STATE" SHADED) ............................................................................................ 375
FIGURE 177. THE STATE MACHINE DIAGRAM FOR THE RECEIVE E3 FRAMER BLOCK'S "FRAME ACQUISITION/MAINTENANCE" ALGORITHM
(WITH THE "OOF STATE" SHADED) ................................................................................................................................ 376
5.3.2.2 THE FRAME-MAINTENANCE MODE - THE OOF AND LOF DECLARATION CRITERIA ............................ 379
5.3.2.3 DECLARING AND CLEARING THE LOS DEFECT CONDITION ................................................................... 380
5.3.2.4 DECLARING AND CLEARING THE AIS DEFECT CONDITION .................................................................... 382
5.3.2.5 DECLARING AND CLEARING THE FERF/RDI DEFECT CONDITION .......................................................... 384
FIGURE 178. FA SIMPLE ILLUSTRATION OF THE "NEAR-END" TERMINAL EQUIPMENT TRANSMITTING THE FERF/RDI INDICATOR TO THE RE-
MOTE TERMINAL EQUIPMENT.......................................................................................................................................... 385
5.3.2.6 DETECTING BIP-4 NIBBLE ERRORS ............................................................................................................ 388
5.3.2.7 DETECTING FEBE/REI (FAR-END BLOCK ERROR/REMOTE ERROR INDICATOR) EVENTS ................. 390
5.3.2.8 DETECTING FAS PATTERN ERRORS ........................................................................................................... 391
5.3.2.9 MONITORING THE STATE OF THE N-BIT IN THE INCOMING E3 DATA STREAM ......................................................... 392
5.3.3 THE RECEIVE LAPD CONTROLLER BLOCK ........................................................................................................ 392
FIGURE 179. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS
BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.751 CLEAR-CHANNEL FRAMER MODE (WITH THE "RECEIVE LAPD CON-
TROLLER" BLOCK HIGHLIGHTED) .................................................................................................................................... 393
FIGURE 180. LAPD MESSAGE FRAME FORMAT ............................................................................................................................ 394
5.3.3.1 RECEIVING STANDARD-TYPE (76 OR 82 BYTE SIZE) LAPD MESSAGES ................................................................. 395
TABLE 47: THE RELATIONSHIP BETWEEN THE CONTENTS WITHIN BITS 4 AND 5 (RXLAPDTYPE[1:0]) AND THE TYPE OF LAPD/PMDL MES-
SAGE RESIDING WITHIN THE RECEIVE LAPD MESSAGE BUFFER ..................................................................................... 398
FIGURE 181. LAPD MESSAGE FRAME FORMAT ............................................................................................................................ 399
FIGURE 182. FLOW-CHART DEPICTING AN APPROACH THAT ONE CAN USE FOR READING OUT THE CONTENTS OF A NEWLY RECEIVED LAPD/
PMDL MESSAGE FROM THE RECEIVE LAPD MESSAGE BUFFER .................................................................................... 400
5.3.3.2 RECEIVING "NON-STANDARD" VARIABLE LENGTH (E.G., UP TO 82 BYTES) LAPD MESSAGES) ............................. 400
FIGURE 183. FLOW-CHART DEPICTING AN APPROACH THAT ONE CAN USE TO READING OUT THE CONTENTS OF THE NEWLY RECEIVE LAPD/
PMDL MESSAGE FROM THE RECEIVE LAPD MESSAGE BUFFER. ................................................................................... 404
5.3.3.3 RECEIVE LAPD CONTROLLER BLOCK INTERRUPTS ............................................................................................. 404
5.3.4 THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK ....................................................................... 404
FIGURE 184. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS
BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.751 CLEAR-CHANNEL FRAMER MODE (WITH THE "RECEIVE OVERHEAD DATA
OUTPUT INTERFACE" BLOCK HIGHLIGHTED) ................................................................................................................... 405
TABLE 48: LIST AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK ..... 406
5.3.4.1 OPERATING THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK USING METHOD 1 - THE "RXOHCLK" METHOD
408
FIGURE 185. ILLUSTRATION OF HOW TO INTERFACE THE "SYSTEM-SIDE TERMINAL EQUIPMENT" TO THE "RECEIVE OVERHEAD DATA OUTPUT
INTERFACE" BLOCK WHEN USING "METHOD 1"................................................................................................................ 408
TABLE 49: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN THE RXOHCLK SIGNAL, SINCE THE RXOHFRAME SIGNAL
WAS LAST SAMPLED "HIGH" TO THE E3 OVERHEAD BIT THAT IS BEING PROCESSED BY THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK ........................................................................................................................................................ 409
5.3.4.2 OPERATING THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK USING METHOD 2 - THE "RXCLK/RXOHENABLE"
METHOD ................................................................................................................................................................. 409
FIGURE 186. ILLUSTRATION OF HOW TO INTERFACE THE "SYSTEM-SIDE TERMINAL EQUIPMENT" TO THE "RECEIVE OVERHEAD DATA OUTPUT
INTERFACE" BLOCK WHEN USING "METHOD 2"................................................................................................................ 410
TABLE 50: THE RELATIONSHIP BETWEEN THE NUMBER OF PULSES IN THE "RXOHENABLE" SIGNAL, SINCE THE RXOHFRAME SIGNAL WAS
LAST SAMPLED "HIGH" TO THE E3 OVERHEAD BIT THAT IS BEING OUTPUT (VIA THE RXOH OUTPUT PIN) BY THE RECEIVE OVER-
HEAD DATA OUTPUT INTERFACE BLOCK......................................................................................................................... 411
FIGURE 187. An illustration of the behavior of Receive Overhead Data Output Interface block signals, whenever the "Method 2" ap-
proach to Data Extraction is used................................................................................................................................411
5.3.5 THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK .......................................................................... 411
FIGURE 188. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS
BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.751 CLEAR-CHANNEL FRAMER MODE (WITH THE "RECEIVE PAYLOAD DATA
OUTPUT INTERFACE" BLOCK HIGHLIGHTED). ................................................................................................................... 412
TABLE 51: LIST AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK ........ 413
5.3.5.1 SERIAL MODE OPERATION OF THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE ................................................ 416
FIGURE 189. AN ILLUSTRATION OF HOW TO INTERFACE THE "SYSTEM-SIDE TERMINAL EQUIPMENT" TO THE "RECEIVE PAYLOAD DATA OUT-
XI
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