XRT79L71 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT79L71' PDF : 609 Pages View PDF
PRELIMINARY
XRT79L71
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
NER.............................................................................................................................................................................. 326
FIGURE 149. A SIMPLE ILLUSTRATION OF THE "NEAR-END" TERMINAL TRANSMITTING THE "UN-ERRED" INDICATION TO THE REMOTE TERMI-
NAL EQUIPMENT ............................................................................................................................................................ 326
FIGURE 150. A SIMPLE ILLUSTRATION OF A "NEAR-END" TERMINAL DETECTING BIP-4 NIBBLE ERRORS WITHIN ITS INCOMING E3 SIGNAL
327
FIGURE 151. A SIMPLE ILLUSTRATION OF THE "NEAR-END" TERMINAL EQUIPMENT TRANSMITTING THE FEBE/REI INDICATOR TO THE RE-
MOTE TERMINAL EQUIPMENT.......................................................................................................................................... 327
5.2.4.5 SETTING THE TRANSMIT E3 FRAMER BLOCK TIMING REFERENCE ........................................................................ 329
5.2.4.6 CONTROLLING THE STATE OF THE N-BIT WITHIN THE OUTBOUND E3 DATA-STREAM ............................................. 331
5.2.5 TRANSMIT DS3/E3 LIU BLOCK - E3 APPLICATIONS ........................................................................................... 331
FIGURE 152. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE TRANSMIT DIRECTION CIRCUITRY, WHENEVER THE XRT79L71
HAS BEEN CONFIGURED TO OPERATE IN THE "E3, ITU-T G.751 CLEAR-CHANNEL FRAMER" MODE (WITH THE "TRANSMIT DS3/E3
FRAMER" BLOCK HIGHLIGHTEDL..................................................................................................................................... 332
FIGURE 153. ILLUSTRATION OF THE TRANSMIT DS3/E3 LIU BLOCK WITHIN THE XRT79L71 .......................................................... 333
5.2.5.1 THE HDB3 ENCODER BLOCK ............................................................................................................................. 333
5.2.5.2 THE JITTER ATTENUATOR BLOCK ....................................................................................................................... 333
FIGURE 154. AN ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE JITTER ATTENUATOR BLOCK ................................... 334
FIGURE 155. A SIMPLISTIC ILLUSTRATION OF THE ROLE/FUNCTION OF THE JITTER ATTENUATOR PLL BLOCK WITHIN THE XRT79L71.335
FIGURE 156. A SIMPLE ILLUSTRATION OF THE JITTER TRANSFER CHARACTERISTICS OF EACH JITTER ATTENUATOR PLL (WITHIN THE
XRT79L71) ................................................................................................................................................................. 336
FIGURE 157. ILLUSTRATION OF THE PHYSICAL ARCHITECTURE OF 2-CHANNEL JITTER ATTENUATOR FIFO ARCHITECTURE WITHIN THE JIT-
TER ATTENUATOR BLOCK.............................................................................................................................................. 337
FIGURE 158. ILLUSTRATION OF THE JITTER ATTENUATOR FIFO AND THE FIFO_WRITE AND FIFO_READ POINTERS. ................... 339
TABLE 44: THE RELATIONSHIP BETWEEN THE STATES OF BITS 2 AND 0 (WITHIN THE "JITTER ATTENUATOR CONTROL" REGISTER) AND THE
(1) ENABLE/DISABLE STATE OF THE JITTER ATTENUATOR, AND (2) THE SIZE OF THE JITTER ATTENUATOR FIFO ............. 341
5.2.5.3 THE TRANSMIT CONTROL BLOCK ........................................................................................................................ 344
5.2.5.4 THE TRANSMIT PULSE SHAPING BLOCK .............................................................................................................. 344
FIGURE 159. E3 PULSE TEMPLATE MEASUREMENT - TAKEN WITH 0 FEET OF CABLE LOSS .............................................................. 345
5.2.5.5 THE TRANSMIT LINE DRIVER BLOCK ................................................................................................................... 345
5.2.5.6 THE TRANSMIT DRIVE MONITOR BLOCK .............................................................................................................. 346
FIGURE 160. A SCHEMATIC DESIGN, DEPICTING THE REQUIRED CONNECTIONS FOR "EXTERNAL" TRANSMIT DRIVE MONITORING ..... 346
FIGURE 161. A SCHEMATIC DESIGN, DEPICTING THE REQUIRED CONNECTIONS FOR "INTERNAL" TRANSMIT DRIVE MONITORING ...... 350
5.2.5.7 INTERFACING THE TRANSMIT DS3/E3 LIU BLOCK TO THE LINE ........................................................................... 352
FIGURE 162. SCHEMATIC DESIGN, DEPICTING HOW TO INTERFACE THE TRANSMIT DS3/E3 LIU BLOCK (OF THE XRT79L71) TO THE LINE
352
5.3 THE RECEIVE DIRECTION .......................................................................................................................... 354
FIGURE 163. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY WHENEVER THE XRT79L71 HAS
BEEN CONFIGURED TO OPERATE IN THE E3 CLEAR-CHANNEL FRAMER MODE ................................................................. 354
5.3.1 THE RECEIVE E3 LIU BLOCK ................................................................................................................................. 354
FIGURE 164. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS
BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.751 CLEAR-CHANNEL FRAMER MODE (WITH THE "RECEIVE DS3/E3 LIU"
BLOCK HIGHLIGHTED). ................................................................................................................................................... 355
FIGURE 165. ILLUSTRATION OF THE RECEIVE DS3/E3 LIU BLOCK WITHIN THE XRT79L71 ............................................................ 356
5.3.1.1 INTERFACING THE RECEIVE DS3/E3 LIU BLOCK TO THE LINE ............................................................................. 356
FIGURE 166. SCHEMATIC DESIGN, DEPICTING HOW TO INTERFACE THE RECEIVE DS3/E3 LIU BLOCK (OF THE XRT79L71) TO THE LINE
357
5.3.1.2 THE AUTOMATIC GAIN CONTROL BLOCK ............................................................................................................. 357
5.3.1.3 THE RECEIVE EQUALIZER BLOCK ........................................................................................................................ 357
5.3.1.4 THE CLOCK AND DATA RECOVERY BLOCK .......................................................................................................... 358
5.3.1.5 THE SFM (SINGLE-FREQUENCY MODE) SYNTHESIZER BLOCK ............................................................................. 361
FIGURE 167. A SIMPLE ILLUSTRATION THAT DEPICTS HOW THE "SFM SYNTHESIZER" BLOCK FUNCTIONS WHENEVER IT HAS BEEN CONFIG-
URED TO OPERATE IN THE "SFM" MODE........................................................................................................................ 362
FIGURE 168. A SIMPLE ILLUSTRATION THAT DEPICTS HOW THE "SFM SYTHESIZER" BLOCK FUNCTIONS WHENEVER IT HAS BEEN CONFIGURED
TO OPERATE IN THE "MULTIPLEXER" MODE.................................................................................................................... 364
5.3.1.6 THE LOS DECLARATION AND CLEARANCE CRITERIA FOR E3 APPLICATIONS ....................................................... 365
FIGURE 169. ILLUSTRATION OF THE SIGNAL LEVELS THAT THE RECEIVE DS3/E3 LIU BLOCK WILL DECLARE AND CLEAR THE LOS DEFECT
CONDITION (FOR E3 APPLICATIONS).............................................................................................................................. 366
FIGURE 170. THE BEHAVIOR THE LOS OUTPUT INDICATOR, IN RESPONSE TO THE LOSS OF SIGNAL, AND THE RESTORATION OF SIGNAL.
367
5.3.1.7 JITTER ATTENUATOR BLOCK .............................................................................................................................. 368
5.3.1.8 THE HDB3 DECODER BLOCK ............................................................................................................................. 369
5.3.1.9 PERFORMANCE CHARACTERISTICS OF THE RECEIVE E3 LIU BLOCK .................................................................... 369
FIGURE 171. ILLUSTRATION OF TEST SET-UP TO PERFORM THE "RECEIVE SENSITIVITY LOW-LEVEL" TEST ..................................... 369
TABLE 45: RECEIVE SENSITIVITY TEST RESULTS (E3 APPLICATIONS) ............................................................................................ 370
FIGURE 172. ILLUSTRATION OF TEST SET-UP USED TO TEST THE XRT79L71 FOR INTERFERENCE MARGIN .................................... 370
TABLE 46: INTERFERENCE MARGIN TEST RESULTS FOR E3 APPLICATIONS ................................................................................... 371
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