XRT79L71IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT79L71IB' PDF : 609 Pages View PDF
XRT79L71
PRELIMINARY
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
REGISTER, AND THE RESULTING F-BIT OOF DECLARATION CRITERIA FOR THE RECEIVE DS3 FRAMER BLOCK ................. 206
TABLE 29: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 0 (M-SYNC ALGO) WITHIN THE RECEIVE DS3 CONFIGURATION AND STATUS
REGISTER, AND THE RESULTING M-BIT OOF DECLARATION CRITERIA FOR THE RECEIVE DS3 FRAMER BLOCK ............... 207
4.3.2.3 DECLARING AND CLEARING THE LOS DEFECT CONDITION ................................................................... 208
4.3.2.4 DECLARING AND CLEARING THE AIS DEFECT CONDITION .................................................................... 210
4.3.2.5 DECLARING AND CLEARING THE DS3 IDLE PATTERN ............................................................................. 214
4.3.2.6 DECLARING AND CLEARING THE FERF INDICATOR ................................................................................ 216
FIGURE 94. A SIMPLE ILLUSTRATION OF THE NEAR-END TERMINAL EQUIPMENT TRANSMITTING THE FERF/RDI INDICATOR TO THE REMOTE
TERMINAL EQUIPMENT ................................................................................................................................................... 217
4.3.2.7 DETECTING P-BIT ERRORS .......................................................................................................................... 218
4.3.2.8 DETECTING CP-BIT ERRORS ........................................................................................................................ 220
4.3.2.9 DETECTING CHANGES IN THE AIC BIT ....................................................................................................... 221
4.3.2.10 DETECTING FEBE (FAR-END BLOCK ERROR) EVENTS .......................................................................... 223
4.3.2.11 DETECTING FRAMING BIT ERRORS .......................................................................................................... 224
4.3.2.12 Receive DS3/E3 Framer Block Interrupts ................................................................................................... 224
4.3.3 RECEIVE LAPD CONTROLLER BLOCK................................................................................................................. 224
FIGURE 95. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS
BEEN CONFIGURED TO OPERATE IN THE DS3 CLEAR-CHANNEL FRAMER MODE (WITH THE RECEIVE LAPD CONTROLLER BLOCK
HIGHLIGHTED)............................................................................................................................................................... 225
FIGURE 96. LAPD MESSAGE FRAME FORMAT .............................................................................................................................. 226
4.3.3.1 RECEIVING STANDARD-TYPE (76 OR 82 BYTE SIZE) LAPD MESSAGES ................................................................. 227
TABLE 30: THE RELATIONSHIP BETWEEN THE CONTENTS WITHIN BITS 4 AND 5 (RXLAPDTYPE[1:0]) AND THE TYPE OF LAPD/PMDL MES-
SAGE RESIDING WITHIN THE RECEIVE LAPD MESSAGE BUFFER ..................................................................................... 230
FIGURE 97. LAPD MESSAGE FRAME FORMAT .............................................................................................................................. 230
FIGURE 98. FLOW-CHART DEPICTING AN APPROACH THAT CAN BE USED FOR READING OUT THE CONTENTS OF A NEWLY RECEIVED LAPD/
PMDL MESSAGE FROM THE RECEIVE LAPD MESSAGE BUFFER .................................................................................... 232
4.3.3.2 RECEIVING NON-STANDARD VARIABLE LENGTH (E.G., UP TO 82 BYTES) LAPD MESSAGES) ................................ 232
FIGURE 99. FLOW-CHART DEPICTING AN APPROACH THAT ONE CAN USE TO READING OUT THE CONTENTS OF THE NEWLY RECEIVE LAPD/
PMDL MESSAGE FROM THE RECEIVE LAPD MESSAGE BUFFER .................................................................................... 236
4.3.3.3 Receive LAPD Controller Block Interrupts ................................................................................................... 236
4.3.4 RECEIVE FEAC CONTROLLER BLOCK................................................................................................................. 236
FIGURE 100. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS
BEEN CONFIGURED TO OPERATE IN THE DS3 CLEAR-CHANNEL FRAMER MODE (WITH THE RECEIVE FEAC CONTROLLER BLOCK
HIGHLIGHTED)............................................................................................................................................................... 237
FIGURE 101. THE BIT-FORMAT OF THE FEAC MESSAGE .............................................................................................................. 237
4.3.4.1 OPERATION OF THE RECEIVE DS3 FEAC CONTROLLER BLOCK .......................................................................... 238
FIGURE 102. FLOW DIAGRAM DEPICTING HOW THE RECEIVE FEAC CONTROLLER BLOCK FUNCTIONS ............................................ 239
4.3.4.2 RECEIVE FEAC CONTROLLER BLOCK INTERRUPTS ............................................................................................. 239
4.3.5 RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK................................................................................ 239
FIGURE 103. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS
BEEN CONFIGURED TO OPERATE IN THE DS3 CLEAR-CHANNEL FRAMER MODE (WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK HIGHLIGHTED)................................................................................................................................... 240
TABLE 31: LIST AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK ..... 241
4.3.5.1 OPERATING THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK USING METHOD 1 - THE RXOHCLK METHOD
242
FIGURE 104. ILLUSTRATION ON HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK WHEN USING METHOD 1 ................................................................................................................... 243
TABLE 32: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN THE RXOHCLK SIGNAL, SINCE THE RXOHFRAME SIGNAL
WAS LAST SAMPLED "HIGH" TO THE DS3 OVERHEAD BIT THAT IS BEING PROCESSED BY THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK ........................................................................................................................................................ 244
4.3.5.2 OPERATING THE RECEIVE OVERHEAD DATA INPUT INTERFACE BLOCK USING METHOD 2 - THE RXCLK/RXOHENABLE
METHOD ................................................................................................................................................................. 245
FIGURE 105. ILLUSTRATION ON HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK WHEN USING METHOD 2 ................................................................................................................... 246
TABLE 33: THE RELATIONSHIP BETWEEN THE NUMBER OF PULSES IN THE RXOHENABLE SIGNAL, SINCE THE RXOHFRAME SIGNAL WAS LAST
SAMPLED "HIGH" TO THE DS3 OVERHEAD BIT THAT IS BEING OUTPUT (VIA THE RXOH OUTPUT PIN) BY THE RECEIVE OVERHEAD
DATA OUTPUT INTERFACE BLOCK .................................................................................................................................. 247
4.3.6 RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK .................................................................................. 248
FIGURE 106. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS
BEEN CONFIGURED TO OPERATE IN THE DS3 CLEAR-CHANNEL FRAMER MODE (WITH THE RECEIVE PAYLOAD DATA OUTPUT IN-
TERFACE BLOCK HIGHLIGHTED)...................................................................................................................................... 249
TABLE 34: LIST AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK ........ 250
4.3.6.1 SERIAL MODE OPERATION OF THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE ................................................ 253
FIGURE 107. AN ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE RECEIVE PAYLOAD DATA OUTPUT
INTERFACE BLOCK OF THE XRT79L71 FOR SERIAL MODE OPERATION ........................................................................... 253
FIGURE 108. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR SERIAL MODE OPERATION
VII
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