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XRT79L71_10 View Datasheet(PDF) - Exar Corporation

Part Name
Description
MFG CO.
'XRT79L71_10' PDF : 609 Pages View PDF
XRT79L71
PRELIMINARY
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
It will detect and flag the occurrence of FEBE/REI Events
It will route all PMDL data to the Receive LAPD Controller block for further processing
It will route all DS3/E3 payload to the Receive High-Speed HDLC Controller block.
1.2.11 The Receive Trail-Trace Message Controller Block (E3, ITU-T G.832 Applications only)
The purpose of the Receive Trail-Trace Message Controller Block is to permit a given terminal equipment to
receive (and extract out) the Trail-Trace Message (also known as "Trail-Access Point Identifier) from the
incoming E3 data-stream (which is being sourced by the remote terminal equipment, via the TR byte, within
each inbound E3, ITU-T G.832 frame. The Receive Trail-Trace Message Controller block will also alert the
Microprocessor (by generating an interrupt) anytime it detects a change in the incoming Trail-Trace Message.
1.2.12 The Receive SSM Controller Block (E3, ITU-T G.832 Applications only)
The purpose of the Receive SSM Controller block is to permit a given terminal equipment to receive (and
extract out) the SSM (Synchronization Status Message) from the remote terminal equipment, via the MA byte,
within each inbound E3, ITU-T G.832 frame.
1.2.13 The Receive FEAC Controller Block (DS3 Applications only)
The purpose of the Receive FEAC Controller block is to permit the user to receive FEAC (Far-End Alarm &
Control) Messages from the remote terminal equipment.
NOTE: The Receive FEAC Controller block is only active if the XRT79L71 is configured to operate in the DS3, C-bit Parity
Framing format.
1.2.14 The Receive LAPD Controller Block
The purpose of the Receive LAPD Controller block is to permit the user to receive LAPD/PMDL (Path
Maintenance Data Link) Messages from the remote terminal equipment. The Receive LAPD Controller block
comes with a Receive LAPD Controller (not to be confused with the Receive High-Speed HDLC Controller
block) and 90 bytes of on-chip RAM (for storage of inbound PMDL Messages) after reception.
NOTE: The role of the Receive LAPD Controller block should not be confused with that of the Receive High-Speed HDLC
Controller block.
1.2.15 The Receive High-Speed HDLC Controller Block
The purpose of the Receive High-Speed HDLC Controller block is to receive the payload data (from the
incoming DS3/E3 data-stream) and perform the following tasks.
To identify the boundaries of incoming HDLC frames (within the incoming DS3/E3 data-stream)
To terminate the Flag Sequence octets within the incoming data-stream
To (optionally) compute and verify the CRC-16 or CRC-32 values that have been appended to the back-end
of these incoming HDLC frames (at the remote terminal equipment) and to flag any occurrences of CRC
errors
To zero-un-stuff the contents within these incoming HDLC frames
To output this HDLC frame data (in a byte-wide manner) via an 8-bit wide Output Data Bus.
1.2.16 The Receive Overhead Data Output Interface Block (not shown in Figure 3).
If the XRT79L71 has been configured to operate in the High-Speed HDLC Controller Mode, then the Receive
Overhead Data Output Interface block will be disabled.
1.2.17
A more detailed Functional/Architectural Description of the XRT79L71, when configured to
operate in the High-Speed HDLC Controller Mode, is in the document
(79L71_Arch_Descr_HDLC.pdf).
(Section 8.0 - Architectural/Functional Description of the XRT79L71 1-Channel DS3/E3 ATM UNI/PPP/Clear-
Channel Framer with LIU IC - High-Speed HDLC Controller Applications).
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