XRT8001
This step configures the XRT8001 to operate in the
“High Speed – Reverse” Mode.
NOTE: If the user wishes to output a clock signal via the
“CLK1” output pin, then he/she should also write a “1” into
the “PL1EN” bit-field within Command Register, CR0.
STEP 3 – Write the binary expression “0000” into
bit-fields D4 through D1, within Command Register,
CR1, as illustrated below.
Command Register, CR1 (Address = 0x01)
D4
D3
D2
D1
D0
M4
M3
M2
M1 PL2EN
0
0
0
0
X
NOTE: If the user wishes to output a clock signal via the
CLK2 output pin, then he/she should also write a “1” into
the “PL2EN” bit-field within Command Register
STEP 4 – Specify the value for “M” (e.g., as in the “M
x 2.048MHz” clock signal) which is to output via the
“CLK1” output pin.
This is accomplished by reviewing Table 3 to deter-
mine the 5 bit binary value which corresponds with the
desired value of “M”. Afterwards, the user should write
this value into Command Register, CR2.
Value of “M”
1
2
4
8
Value to be written into the
Command Register, CR2
0000x
0001x
001xx
x1xx or 1xxx
Table 12: Relationship between the value of
“M”, and Value to be written into Command
Register, CR2 to configure the “CLK1” output
frequency
STEP 5 – Specify the value for “M” (e.g., as in the
“M x 2.048MHz” clock signal) which is to output via
the “CLK2” output pin.
This is accomplished by reviewing Table 4 to deter-
mine the 5 bit binary value corresponding with the
desired value of “M”. Afterwards, the user should write
this value into Command Register, CR3.
Value of
“M”
1
2
4
8
Value to be written into the
Command Register, CR3
0000x
0001x
001xx
x1xx or 1xxx
Table 13, The Relationship between the value of
“M”, and Value to be written into Command
Register, CR2 to configure the “CLK2” output
frequency
STEP 6 – Enable the desired output signals:
“SYNC”, “CLK1”, “CLK2” and “LOCKDET”.
This is accomplished by writing a “1” into the corre-
sponding bit-fields, within Command Register CR4, as
illustrated below.
Command Register, CR4 (Address = 0x04)
D4
D3
D2
D1
D0
SYNCEN CLK1EN CLK2EN LDETDIS2 LDETDIS1
1
1
1
0
0
Rev. 1.01
37