XRT8001IP View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT8001IP' PDF : 48 Pages View PDF
XRT8001
7.1 Synthesizing an “M x 2.048MHz” clock signal,
such that “M” can take on the value of “1”, “2”, “4”,
or “8” with a clock signal of 2.048MHz
Figure 21 presents a possible approach that can be
used. In this example, the user takes the 2.048MHz
clock signal, and runs it through an external “Divide-
by-32” counter (which is realized with two
74AHCT193). This “Divide-by-32” counter generates
a 64kHz clock signal, which is applied to the “FIN”
input pin of the XRT8001.
2.048MHz_CLOCK
+5V
R1
1K
U2
15
1
10
9
A
B
C
D
QA
QB
QC
QD
3
2
6
7
5
12
4 UP
CO 13
11
14
DN
LOAD
CLR
BO
74AHCT193
If the user configures the XRT8001 WAN Clock to
operate in the “High Speed – Reverse” Mode, then
it will accepts a 64kHz clock signal (via the FIN
input) and generates an “M x 2.048MHz” clock
signal via both the CLK1 and CLK2 outputs.
NOTES:
1. In this configuration, “M” can be configured to be of
value “1”, “2”, “4” or “8”.
2. The steps required to configure the XRT8001 into the
“High Speed – Reverse” Mode are presented below.
Clear_Counter
Serial_Clock
Serial_Data_Out
Serial_Data_In
XRT8000_Select
U3
15
1
10
9
A
B
C
D
QA
QB
QC
QD
3
2
6
7
5
12
4 UP
CO 13
11 DN
BO
14
LOAD
CLR
74AHCT193
64kHz Clock Signal
U1
3 FIN
18
1
16
SCLK
SDO
17 SDI
CS
8 MSB
XRT8001
CLK1 6
13
CLK2
11
LOCKDET
M x 2.048MHz_CLOCK
M x 2.048MHz_CLOCK
WAN_CLOCK_PLL_LOCK_STATUS
Figure 21: Circuit that inputs a 2.048MHz clock and generates a “M” x 2.048MHz clock
7.2 Configuring the XRT8001 WAN Clock to operate
in the “High Speed – Reverse” Mode.
The following is a “six-step” procedure to configure the
XRT8001 WAN Clock into the “High Speed – Reverse”
Mode.
STEP 1 – Configure the XRT8001 to operate in the
“SLAVE” Mode, by pulling the “MSB” input pin (pin 8)
to GND (low).
STEP 2 – Write the binary expression “1101” into bit-
fields D4 through D1, within Command Register, CR0,
as indicated below.
Command Register, CR1 (Address = 0x01)
D4
D3
D2
D1
D0
M4
M3
M2
M1 PL2EN
1
1
0
1
X
Rev. 1.01
36
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