XRT83D10IWTR-F View Datasheet(PDF) - Exar Corporation

Part Name

Description

MFG CO.

XRT83D10IWTR-F

SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT

Exar Corporation 

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XRT83D10

SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT

REV. 1.0.3

FIGURE 7. ITU G.703 PULSE TEMPLATE

269 ns

(244 + 25)

V = 100%

194 ns

(244 – 50)

xr

Nominal pulse

50%

0%

244 ns

219 ns

(244 – 25)

488 ns

(244 + 244)

Note – V corresponds to the nominal peak value.

1.3 JITTER ATTENUATOR

To reduce frequency jitter in the transmit clock or receive clock, a crystal-less jitter attenuator is provided. The

jitter attenuator can be selected either in the transmit or receive path or it can be disabled as shown in Table 8.

TABLE 8: JITTER ATTENUATOR SELECTION

JITTER ATTENUATOR CONNECTIVITY

MODE 1

Bypass (Disabled)

0

Transmit Path

0

Receive Path

1

Test Mode

1

MODE 2

0

1

0

1

1.3.1 FIFO Overflow Signal (FOFS):

A FIFO overflow Signal (FOFS = 1) is indicated if the phase jitter exceeds the tolerance of the jitter attenuator.

When FOFS is "High", jitter attenuator bandwidth is increased to track the short term jitter and no data error will

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