XRT83L314IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83L314IB' PDF : 84 Pages View PDF
XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
TABLE 26: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION
BIT
NAME
CHANNEL 0-13 (0X01H-0XD1H)
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
RxTSEL Receive Termination Select
R/W
0
Upon power up, the receiver is in "High" impedance. RxTSEL is
used to switch between the internal termination and "High" imped-
ance.
0 = "High" Impedance
1 = Internal Termination
D6
TxTSEL Transmit Termination Select
R/W
0
Upon power up, the transmitter is in "High" impedance. TxTSEL is
used to switch between the internal termination and "High" imped-
ance.
0 = "High" Impedance
1 = Internal Termination
D5
TERSEL1 Receive Line Impedance Select
R/W
0
D4
TERSEL0 TERSEL[1:0] are used to select the line impedance for T1/J1/E1.
0
00 = 100Ω
01 = 110Ω
10 = 75Ω
11 = 120Ω
D3
RxJASEL Receive Jitter Attenuator Select
R/W
0
RxJASEL is used to enable the receiver jitter attenuator. By
default, RxJASEL is disabled.
0 = Disabled
1 = Enabled
D2
TxJASEL Transmit Jitter Attenuator Select
R/W
0
TxJASEL is used to enable the transmitter jitter attenuator. By
default, TxJASEL is disabled.
0 = Disabled
1 = Enabled
D1
JABW Jitter Bandwidth (E1 Mode Only, T1 is permanently set to 3Hz) R/W
0
The jitter bandwidth is a global setting that is applied to both the
receiver and transmitter jitter attenuator.
0 = 10Hz
1 = 1.5Hz
D0
FIFOS FIFO Depth Select
R/W
0
The FIFO depth select is used to configure the part for a 32-bit or
64-bit FIFO (within the jitter attenuator blocks). The delay of the
FIFO is equal to ½ the FIFO depth. This is a global setting that is
applied to both the receiver and transmitter FIFO.
0 = 32-Bit
1 = 64-Bit
54
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