XRT83L34
xr
REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
THE MICROPROCESSOR INTERFACE
XRT83L34 is equipped with a microprocessor interface for easy device configuration. The parallel port of the
XRT83L34 is compatible with both the Intel-Asynchronous and the Motorola-Asynchronous address and data
buses. The XRT83L34 has an 7-bit address A[6:0] input and 8-bit bi-directional data bus D[7:0].
THE PINS OF THE MICROPROCESSOR INTERFACE
Table 16 presents a list and a brief description of each of the pins that make up the Microprocessor Interface block, within
the XRT83L34 device.
D[7:0]
A[6:0]
µPTS1
µPTS2
µPCLK
TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION
Bi-Directional Data Bus pins:
These pins are used to drive and receive data over the bi-directional data bus, whenever the Micro-
processor performs READ or WRITE operations with the Microprocessor Interface of the XRT83L34
device.
Address Bus Input pins:
These input pins permit the Microprocessor to identify on-chip registers (within the XRT83L34 device)
whenever it performs READ and WRITE operations with the XRT83L34 device.
Microprocessor Type Select:
µPTS2
0
0
µPTS1
0
1
µP Type
Intel Asynchronous Mode
Motorola Asynchronous Mode
µPTS2 should be tied to GND. µPTS1 selects the microprocessor type.
Microprocessor Clock Input: This pin should be tied to GND for asychronous microprocessor inter-
face.
NOTE: This pin is internally pulled “Low” for asynchronous microprocessor operation when no clock is
present.
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