XRT83L38IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
XRT83L38IB
Exar Corporation
'XRT83L38IB' PDF : 87 Pages View PDF
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
In Hardware mode, RXTSEL (Pin 83) can be tied “High” to select internal termination mode for all receive
channels or tied “Low” to select external termination mode. Individual channel control can only be done in Host
mode. By default the XRT83L38 is set for external termination mode at power up or at Hardware reset.
TABLE 6: RECEIVE TERMINATION CONTROL
RXTSEL
RX TERMINATION
0
EXTERNAL
1
INTERNAL
In Host mode, bit 7 in the appropriate channel register, (Table 20, “Microprocessor Register #1, Bit
Description,” on page 51), is set “High” to select the internal termination mode for that specific receive channel.
FIGURE 13. SIMPLIFIED DIAGRAM FOR THE INTERNAL RECEIVE AND TRANSMIT TERMINATION MODE
TPOS
TNEG
TCLK
TX
Line Driver
RPOS
RNEG
RCLK
RX
Equalizer
Channel _n
R int
TTIP
0.68µ F
1
T1 5
TRING
R int
RTIP
R int
RRING
4
8
1:2
5
T2 1
8
4
1:1
TTIP
75 Ω , 100 Ω
110 Ω or 120 Ω
TRING
RTIP
75 Ω , 100 Ω
110 Ω or 120 Ω
RRING
If the internal termination mode (RXTSEL = “1”) is selected, the effective impedance for E1, T1 or J1 can be
achieved either with an internal resistor or a combination of internal and external resistors as shown in Table 7.
NOTE: In Hardware mode, pins RXRES[1:0] control all channels.
RXTSEL
0
1
1
1
TERSEL1
x
0
0
1
TABLE 7: RECEIVE TERMINATIONS
TERSEL0 RXRES1 RXRES0
Rext
x
x
x
Rext
0
0
0
∞
1
0
0
∞
0
0
0
∞
Rint
∞
100Ω
110Ω
75Ω
MODE
T1/E1/J1
T1
J1
E1
32
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