XRT83SH38
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
FIGURE 34. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
CS
SCLK
SDI
t21
t22
t23
ADDR 6
t26
t24
t25
ADDR 7
R/w
REV. 1.0.7
t28
CS
SCLK
t29
SDO Hi-Z
D0
D1
D2
Don’t Care (Read mode)
SDI
t31
D7
TABLE 13: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V± 5% AND LOAD = 10PF)
SYMBOL
PARAMETER
MIN.
TYP.
MAX
UNITS
t21 CS Low to Rising Edge of SClk
5
ns
t22 SDI to Rising Edge of SClk
5
ns
t23 SDI to Rising Edge of SClk Hold Time
5
ns
t24 SClk "Low" Time
20
ns
t25 SClk "High" Time
20
ns
t26 SClk Period
40
ns
t28 CS Inactive Time
40
ns
t29 Falling Edge of SClk to SDO Valid Time
5
ns
t31 Rising edge of CS to High Z
5
ns
43