XRT83SH38
REV. 1.0.7
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
6.2 Parallel Microprocessor Interface Block
The Parallel Microprocessor Interface section supports communication between the local microprocessor (µP)
and the LIU. The XRT83SH38 supports an Intel asynchronous interface, Motorola 68K asynchronous, and an
Intel/Motorola interface. The microprocessor interface is selected by the state of the µPTS[1:0] input pins.
Selecting the microprocessor interface is shown in Table 14.
TABLE 14: SELECTING THE MICROPROCESSOR INTERFACE MODE
µPTS[1:0]
MICROPROCESSOR MODE
0h (00)
Intel 68HC11, 8051, 80C188
(Asynchronous)
1h (01)
Motorola 68K (Asynchronous)
2h (10)
Intel x86 (Synchronous)
3h (11)
860 Motorola (Synchronous)
The XRT83SH38 uses multipurpose pins to configure the device appropriately. The local µP configures the
LIU by writing data into specific addressable, on-chip Read/Write registers. The microprocessor interface
provides the signals which are required for a general purpose microprocessor to read or write data into these
registers. The microprocessor interface also supports polled and interrupt driven environments. A simplified
block diagram of the microprocessor is shown in Figure 35.
FIGURE 35. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK
CS
WR_R/W
RD_DS
ALE
ADDR[7:0]
DATA[7:0]
µPclk
µPType [1:0]
Reset
RDY
INT
Microprocessor
Interface
44