XRT83SH38ES View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SH38ES' PDF : 78 Pages View PDF
XRT83SH38
REV. 1.0.7
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
4.0 TRANSMIT PATH LINE INTERFACE
The transmit path of the XRT83SH38 LIU consists of 8 independent T1/E1/J1 transmitters. The following
section describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A
simplified block diagram of the transmit path is shown in Figure 16.
FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH
TCLK
TPOS
TNEG
HDB3/B8ZS
Encoder
Tx Jitter
Attenuator
Timing
Control
Tx Pulse Shaper
& Pattern Gen
Line Driver
TTIP
TRING
4.1 TCLK/TPOS/TNEG Digital Inputs
In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG has
no function and can be left unconnected. The XRT83SH38 can be programmed to sample the inputs on either
edge of TCLK. By default, data is sampled on the falling edge of TCLK. To sample data on the rising edge of
TCLK, set TCLKE to "1" in the appropriate global register. Figure 17 is a timing diagram of the transmit input
data sampled on the falling edge of TCLK. Figure 18 is a timing diagram of the transmit input data sampled on
the rising edge of TCLK. The timing specifications are shown in Table 7.
FIGURE 17. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK
TCLKR
TCLKF
TCLK
TPOS
or
TNEG
TSU
THO
FIGURE 18. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK
TCLKF
TCLKR
TCLK
TPOS
or
TNEG
TSU
THO
28
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