XRT83SL216
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
1.7 ARAOS (Automatic Receive All Ones)
If ARAOS is enabled in the appropriate channel register and an RLOS condition occurs, the Receiver outputs
will generate an All Ones pattern using MCLK as reference. When RLOS clears, the All Ones pattern ends and
the Receive path returns to normal operation.
FIGURE 7. SIMPLIFIED BLOCK DIAGRAM OF THE ARAOS FUNCTION
RPOS
RNEG
Rx
All "1's"
Generator
Timing derived
from MCLK
ARAOS
RLOS
1.8 RPOS/RNEG/RCLK
The digital output data can be programmed to either single rail or dual rail formats. Figure 8 is a timing diagram
of a repeating "0011" pattern in single-rail mode. Figure 9 is a timing diagram of the same fixed pattern in dual
rail mode.
FIGURE 8. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN
RCLK
RPOS
0
0
1
1
FIGURE 9. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN
RCLK
RPOS
0
1
RNEG
0
1
0
0
18