XRT83SL314IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SL314IB' PDF : 83 Pages View PDF
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14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SL314
REV. 1.0.1
NOTE: The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the
interrupt pin.
TABLE 30: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION
CHANNEL 0-13 (0X05H-0XD5H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D4
LCV/OF Line Code Violation / Counter Overflow
RO
0
This bit serves a dual purpose. By default, this bit monitors the line
code violation activity. However, if bit 7 in register 0xE5h is set to a
"1", this bit monitors the overflow status of the internal LCV
counter. An interrupt will not occur unless the LCV/OFIE is set to
"1" in the channel register 0x04h and GIE is set to "1" in the global
register 0xE0h.
0 = No Alarm
1 = A line code violation, bipolar violation, or excessive zeros has
occurred
D3
NLCD Network Loop Code Detection
RO
0
The network loop code detection is always active regardless if the
interrupt generation is disabled. This bit indicates the NLCD activ-
ity. An interrupt will not occur unless the NLCDIE is set to "1" in the
channel register 0x04h and GIE is set to "1" in the global register
0xE0h.
0 = No Alarm
1 = Network loop code detected according to the mode selected in
channel register 0x03h
D2
AISD Alarm Indication Signal
RO
0
The alarm indication signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the AIS
activity. An interrupt will not occur unless the AISIE is set to "1" in
the channel register 0x04h and GIE is set to "1" in the global regis-
ter 0xE0h.
0 = No Alarm
1 = An all ones signal is detected
D1
RLOS Receiver Loss of Signal
RO
0
The receiver loss of signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the RLOS
activity. An interrupt will not occur unless the RLOSIE is set to "1"
in the channel register 0x04h and GIE is set to "1" in the global
register 0xE0h.
0 = No Alarm
1 = An RLOS condition is present
D0
QRPD Quasi Random Pattern Detection
RO
0
The quasi random pattern detection is always active regardless if
the interrupt generation is disabled. This bit indicates that a QRPD
has been detected. An interrupt will not occur unless the QRPDIE
is set to "1" in the channel register 0x04h and GIE is set to "1" in
the global register 0xE0h.
0 = No Alarm
1 = A QRP is detected
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