XRT83SL34 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SL34' PDF : 80 Pages View PDF
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.8
MICROPROCESSOR INTERFACE
SIGNAL NAME
HW_HOST
WR_R/W
TAOS_0
RD_DS
TAOS_1
ALE_AS
TAOS_2
CS
TAOS_3
RDY_DTACK
RXMUTE
PIN #
68
69
69
70
70
71
71
72
72
73
73
TYPE
I
I
I
I
I
O
I
DESCRIPTION
Mode Control Input
This pin selects Hardware or Host mode. Leave this pin unconnected or tie
“High” to select Hardware mode.
For Host mode, this pin must be tied “Low”.
NOTE: Internally pulled “High” with a 50kΩ resistor.
Write Input (Read/Write) - Host mode
Intel bus timing: A “Low” pulse on WR selects a write operation when CS
pin is “Low”.
Motorola bus timing: A “High” pulse on R/W selects a read operation and a
“Low” pulse on R/W selects a write operation when CS is “Low”.
Transmit All “Ones” Channel_0 - Hardware Mode
See “Transmit All Ones for Channel _0 - Hardware mode” on page 7.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
Read Input (Data Strobe) - Host Mode
Intel bus timing: A “Low” pulse on RD selects a read operation when the CS
pin is “Low”.
Motorola bus timing: A “Low” pulse on DS indicates a read or write opera-
tion when the CS pin is “Low”.
Transmit All “Ones” Channel_1 - Hardware Mode
See “Transmit All Ones for Channel _0 - Hardware mode” on page 7.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
Address Latch Input (Address Strobe) - Host Mode
Intel bus timing: The address inputs are latched into the internal register on
the falling edge of ALE.
Motorola bus timing: The address inputs are latched into the internal regis-
ter on the falling edge of AS.
Transmit All “Ones” Channel_2 - Hardware Mode
See “Transmit All Ones for Channel _0 - Hardware mode” on page 7.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
Chip Select Input - Host Mode
This signal must be “Low” in order to access the parallel port.
Transmit All “Ones” Channel_3 - Hardware Mode
See “Transmit All Ones for Channel _0 - Hardware mode” on page 7.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
Ready Output (Data Transfer Acknowledge Output) - Host Mode
Intel bus timing: RDY is asserted “High” to indicate the device has com-
pleted a read or write operation.
Motorola bus timing: DTACK is asserted "Low" to indicate the device has
completed a read or write cycle.
Receive Muting - Hardware mode
See “Receive Muting - Hardware mode” on page 5.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
8
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