XRT83SL38ES View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
XRT83SL38ES
Exar Corporation
'XRT83SL38ES' PDF : 89 Pages View PDF
XRT83SL38
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.1.0
PRELIMINARY
TABLE 36: MICROPROCESSOR REGISTER #129, BIT DESCRIPTION
D1
EXLOS Extended LOS: Writing a “1” to this bit extends the number of R/W
0
zeros at the receive input of each channel before RLOS is
declared to 4096 bits. Writing a “0” reverts to the normal mode
(175+75 bits for T1 and 32 bits for E1).
D0
ICT
In-Circuit-Testing: Writing a “1” to this bit configures all the
R/W
0
output pins of the chip in high impedance mode for In-Circuit-
Testing. Setting the ICT bit to “1” is equivalent to connecting
the Hardware ICT pin 88 to ground.
TABLE 37: MICROPROCESSOR REGISTER #130, BIT DESCRIPTION
REGISTER ADDRESS
10000010
BIT #
NAME
FUNCTION
REGISTER
TYPE
RESET
VALUE
D7
TXONCNTL Transmit On Control:
R/W
0
In Host mode, setting this bit to “1” transfers the control of the
Transmit On/Off function to the TXON_n Hardware control
pins.
NOTE: This provides a faster On/Off capability for redundancy
application.
D6
TERCNTL Termination Control.
R/W
0
In Host mode, setting this bit to “1” transfers the control of the
RXTSEL to the RXTSEL Hardware control pin.
NOTE: This provides a faster On/Off capability for redundancy
application.
D5-D4
Reserved
69
Share Link: 