XRT83SL38
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.1.0
PRELIMINARY
MICROPROCESSOR INTERFACE I/O TIMING
INTEL INTERFACE TIMING - ASYNCHRONOUS
The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD),
Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum ex-
ternal glue logic and is compatible with the timings of the 8051 or 80C188 with an 8-16 MHz clock frequency,
and with the timings of x86 or i960 family or microprocessors. The interface timing shown in Figure 28 and
Figure 30 is described in Table 51.
FIGURE 28. INTEL ASYNCHRONOUS PROGRAMMED I/O INTERFACE TIMING
ALE_AS
A D D R [6 :0 ]
CS
D A T A [7 :0 ]
RD_DS
W R _R /W
RDY_DTACK
t0
t5
t1
READ OPERATION
Valid Address
Valid Data for Readback
t2
WRITE OPERATION
t0
t5
Valid Address
Data Available to W rite Into the LIU
t3
t4
TABLE 51: ASYNCHRONOUS MODE 1 - INTEL 8051 AND 80188 INTERFACE TIMING
SYMBOL
PARAMETER
MIN
MAX
t0
Valid Address to CS Falling Edge
t1
CS Falling Edge to RD Assert
t2
RD Assert to RDY Assert
NA
RD Pulse Width (t2)
0
-
65
-
-
50
50
-
t3
CS Falling Edge to WR Assert
t4
WR Assert to RDY Assert
NA
WR Pulse Width (t2)
65
-
-
50
50
-
t5
CS Falling Edge to AS Falling Edge
0
-
Reset pulse width - both Motorola and Intel Operations (see Figure 30)
t9
Reset pulse width
30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
81