XRT83SL38
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.1.0
PRELIMINARY
TABLE 50: AC ELECTRICAL CHARACTERISTICS
VDD=3.3V±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED
PARAMETER
SYMBOL
MIN.
TYP.
E1 MCLK Clock Frequency
-
2.048
T1 MCLK Clock Frequency
-
1.544
MCLK Clock Duty Cycle
40
-
MCLK Clock Tolerance
-
±50
TCLK Duty Cycle
TCDU
30
50
Transmit Data Setup Time
TSU
50
-
Transmit Data Hold Time
THO
30
-
TCLK Rise Time(10%/90%)
TCLKR
-
-
TCLK Fall Time(90%/10%)
TCLKF
-
-
RCLK Duty Cycle
RCDU
45
50
Receive Data Setup Time
RSU
150
-
Receive Data Hold Time
RHO
150
-
RCLK to Data Delay
RDY
-
-
RCLK Rise Time(10% to 90%) with
RCLKR
-
-
25pF Loading.
RCLK Fall Time(90% to 10%) with
25pF Loading.
RCLKF
MAX.
60
-
70
-
-
40
40
55
-
-
40
40
40
UNITS
MHz
MHz
%
ppm
%
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
FIGURE 26. TRANSMIT CLOCK AND INPUT DATA TIMING
TCLKR
TCLKF
TCLK
TPOS/TDATA
or
TNEG
TSU
THO
79