XRT91L30IQ-F View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L30IQ-F' PDF : 39 Pages View PDF
XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
xr
REV. 1.0.1
Table 15 provides configuration for selecting the loop timing and clock recovery modes. The use of the on-chip
CDR or an external recovered clock in loop timing applications is shown in Figure 16.
TABLE 15: LOOP TIMING AND CLOCK RECOVERY CONFIGURATIONS
CDRDIS
LOOPTIME
TRANSMIT CLOCK SOURCE
RECEIVE CLOCK SOURCE
0
0
Clock Multiplier Unit
CDR Enabled.
Clock and Data recovery by internal CDR
0
1
Internal CDR
CDR Enabled.
Clock and Data recovery by internal CDR
CDR Disabled.
Externally recovered Receive Clock from
1
0
Clock Multiplier Unit
XRXCLKIP/N
622.08/155.52 Mbps data on RXIP/N sampled at
rising edge of XRXCLKIP/N
CDR Disabled.
Externally recovered Receive Clock from
1
1
External CDR thru XRXCLKIP/N
XRXCLKIP/N
622.08/155.52 Mbps data on RXIP/N sampled at
rising edge of XRXCLKIP/N
FIGURE 16. LOOP TIMING MODE USING INTERNAL CDR OR AN EXTERNAL RECOVERED CLOCK
REFCLKP
REFCLKN
TTLREFCLK
TXDI[7:0]
TXPCLK_IO
PIO_CTRL
LOOPTIME
CDRDIS
8
0
ENB
1
ENB
RXDO[7:0]
~
RXPCLKO
8
Div by 8
622.08/
155.52MHz
CMU
XRT91L30
MUX
PISO
Div by
8
DATA
CLK to Retimer
Retimer
CLK
SIPO
DATA
Clk
CDR
Data
TXOP
TXON
XRXCLKIP
XRXCLKIN
RXIP
RXIN
~
26
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