XRT91L31 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L31' PDF : 41 Pages View PDF
XRT91L31
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
2.3 Receive Clock and Data Recovery
The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the Differential LVPECL
receiver and generates a clock that is the same frequency as the incoming data. The clock recovery can either
utilize the transmitter’s CMU reference clock from either REFCLKP/N or TTLREFCLK (+/- 20ppm) or it can use
independent clock source CDRAUXREFCLK (+/- 200ppm) to train and monitor its clock recovery PLL. Initially
upon startup, the PLL locks to the local reference clock. Once this is achieved, the PLL then attempts to lock
onto the incoming receive data stream. Whenever the recovered clock frequency deviates from the local
reference clock frequency by more than approximately ±500 ppm, the clock recovery PLL will switch and lock
back onto the local reference clock. Whenever a Loss of Lock or a Loss of Signal event occurs, the CDR will
continue to supply a receive clock (based on the local reference) to the framer/mapper device. When the
LOSEXT is asserted by the optical module or when LOS is detected, the receive parallel data output will be
forced to a logic zero state for the entire duration that a LOS condition is detected. This acts as a receive data
mute upon LOS function to prevent random noise from being misinterpreted as valid incoming data. When the
LOSEXT becomes inactive and the recovered clock is determined to be within ±500 ppm accuracy with respect
to the local reference source and LOS is no longer declared, the clock recovery PLL will switch and lock back
onto the incoming receive data stream. Table 7 shows Clock and Data Recovery reference clock settings.
Table 8 specifies the Clock and Data Recovery Unit performance characteristics.
TABLE 7: CLOCK DATA RECOVERY UNIT REFERENCE CLOCK SETTINGS
CMUFREQSEL CDRREFSEL
0
0
0
0
1
0
1
0
X
1
X
1
STS12/
STS3
0
1
0
1
0
1
REFCLKP/N1OR
TTLREFCLK1
FREQUENCY (MHZ)
CDRAUXREFCLK2
FREQUENCY (MHZ)
77.76 MHz
not used
77.76 MHz
not used
19.44 MHz
not used
19.44 MHz
not used
not referenced by CDR
77.76 MHz
not referenced by CDR
77.76 MHz
CDR OUTPUT
FREQUENCY (MHZ)
155.52
622.08
155.52
622.08
155.52
622.08
1Requires frequency accuracy better than +/- 20 ppm in order for the transmitted data rate frequency
to have the necessary accuracy required for SONET systems.
2CDRAUXREFCLK requires accuracy of 77.76 MHz +/- 200 ppm.
TABLE 8: CDR AUXREFCLK REFERENCE FREQUENCY REQUIREMENT FOR CLOCK AND DATA RECOVERY
NAME
REFDUTY
REFTOL
PARAMETER
Reference clock duty cycle
Reference clock frequency tolerance
MIN
TYP
MAX UNITS
40
60
%
-200
+200 ppm
2.3.1 Internal Clock and Data Recovery Bypass
Optionally, the internal CDR unit can be disabled and bypassed in lieu of an externally recovered clock.
Asserting the CDRDIS "High" disables the internal Clock and Data Recovery unit and the received serial data
bypasses the integrated CDR block. RXINP/N is then sampled on the rising edge of the externally recovered
17
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