XRT91L31 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L31' PDF : 41 Pages View PDF
XRT91L31
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
2.8 Receive Parallel Output Interface
The 8-bit Single-Ended LVTTL running at 77.76 Mbps (STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) parallel
data output of the receive path is used to interface to a SONET Framer/ASIC synchronized to the recovered
clock. A simplified block diagram is shown in Figure 9.
FIGURE 9. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK
SONET Framer/ASIC
RXDO[7:0]
8
RXPCLKO
XRT91L31
STS-12/STM-4
or
STS-3/STM-1
Transceiver
2.9 Disable Parallel Receive Data Output Upon LOS
The parallel receiver outputs are automatically pulled "Low" or forced to a logic state of "0" during a LOS
condition (DLOOP or ALOOP not activated) to prevent data chattering unless LOS detection is disabled by
asserting DLOSDIS and keeping LOSEXT input pin "high." In addition, the user can also assert LOSEXT input
pin from the optical module to force an LOS and mute the parallel receiver outputs as well when DLOSDIS is
not enabled (LOW), see Figure 7).
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