XRT91L32IQ-F View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L32IQ-F' PDF : 37 Pages View PDF
xr
REV. 1.0.2
XRT91L32
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
TABLE 6: CLOCK AND DATA RECOVERY UNIT PERFORMANCE
NAME
REFDUTY
REFJIT
REFJIT
REFTOL
TOLJIT
OCLKFREQ
OCLKDUTY
PARAMETER
Reference clock duty cycle
Reference clock jitter (rms) with 19.44 MHz reference1
Reference clock jitter (rms) with 77.76 MHz reference1
Reference clock frequency tolerance2
Input jitter tolerance with 1 MHz < f < 20 MHz PRBS pattern
Frequency output
Clock output duty cycle
MIN
TYP
MAX UNITS
40
60
%
5
ps
13
ps
-20
+20 ppm
0.3
0.4
UI
620
624 MHz
40
60
%
Jitter specification is defined using a 12kHz to 1.3/5MHz LP-HP single-pole filter.
1These reference clock jitter limits are required for the outputs to meet SONET system level jitter requirements (<10 mUIrms).
2Required to meet SONET output frequency stability requirements.
2.3.1 Internal Clock and Data Recovery Bypass
Optionally, the internal CDR unit can be disabled and bypassed in lieu of an externally recovered clock.
Asserting the CDRDIS "High" disables the internal Clock and Data Recovery unit and the received serial data
bypasses the integrated CDR block. RXINP/N is then sampled on the rising edge of the externally recovered
differential clock XRXCLKIP/N coming from the optical module or an external clock recovery unit. Figure 5
shows the possible internal paths of the recovered clock and data.
FIGURE 5. INTERNAL CLOCK AND DATA RECOVERY BYPASS
CDRDIS
Div by 8 CLOCK
Parallel DATA
8
CLOCK
SIPO
DATA
Clk
CDR
Data
XRXCLKIP
XRXCLKIN
RXIP
RXIN
15
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