XRT91L32
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
xr
REV. 1.0.2
3.2 Transmit Parallel Data Input Timing
When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in
Figure 12 and Table 10, Table 11.
FIGURE 12. TRANSMIT PARALLEL INPUT TIMING
Transmit Parallel
Clock driven by
XRT91L30 Device
TXPCLK_IO
Transmit Parallel Clock Output
tTXPCLK_IO
TXDI[7:0]
tTXDI_SU
tTXDI_HD
TABLE 10: TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION)
SYMBOL
tTXPCLK_IO
tTXDI_SU
tTXDI_HD
PARAMETER
Transmit Clock Output period
Transmit data setup time with respect to TXPCLK_IO
Transmit data hold time with respect to TXPCLK_IO1
MIN
TYP
MAX UNITS
12.86
ns
1.0
ns
1.0
ns
TABLE 11: TRANSMIT PARALLEL DATA INPUT TIMING (STS-3/STM-1 OPERATION).
SYMBOL
tTXPCLK_IO
tTXDI_SU
tTXDI_HD
PARAMETER
Transmit Clock Output period
Transmit data setup time with respect to TXPCLK_IO
Transmit data hold time with respect to TXPCLK_IO1
MIN
TYP
MAX UNITS
51.44
ns
1.0
ns
1.0
ns
22