XRT91L81IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L81IB' PDF : 40 Pages View PDF
PRELIMINARY
XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
3.2 Transmit Parallel Input Data Timing
When applying parallel input data to the transmitter, the setup and hold times should be followed as shown in
Figure 8 and Table 4.
FIGURE 8. TRANSMIT PARALLEL INPUT TIMING
TxCLKIP/N
TXTS
TxDI[3:0]P/N
TXTH
TABLE 4: TRANSMIT PARALLEL INPUT DATA TIMING SPECIFICATIONS
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN.
TXTS TxCLKIP/N "High" to data setup time
300
TXTH TxCLKIP/N "High" to data hold time
300
TXDTY TxCLKIP/N Duty Cycle
40
TYP.
MAX. UNITS
pS
pS
60
%
CONDITIONS
3.3 Transmit FIFO
The Parallel Interface also includes a 4x9 FIFO that can be used to eliminate difficult timing issues between the
input transmit clock and the clock derived from the CMU. The use of the FIFO permits the system to tolerate an
arbitrary amount of delay and jitter between TXCLKOP/N and TXCLKIP/N. The FIFO can be initialized when
FIFO_RESET is asserted and held low for 10 cycles of the TXCLKO clock. Once the FIFO is centered, the
delay between TXCLKO and TXCLKI can decrease or increase up to two periods of the low-speed clock
(TXCLKO). Should the delay exceed this amount, the read and write pointers will point to the same word in the
FIFO resulting in a loss of transmitted data (FIFO overflow). In the event of a FIFO overflow the FIFO control
logic will initiate an OVERFLOW signal that can be used by an external controller to issue a RESET signal. The
chip under the control of the FIFO_AUTORST pin can automatically recover from an overflow condition. When
the FIFO_AUTORST input is set to a "High" level, once an overflow condition is detected, the chip will set the
OVERFLOW pin to a high level and will automatically reset and center the FIFO. For the transparent mode of
operation (no FIFO), the RESET should be held at a constant "High" state.
3.4 FIFO Calibration Upon Power Up
It is required that the FIFO_RST pin be pulled "High" for 10 TXCLK cycles to flush out the FIFO after the device
is powered on. If the FIFO experiences an Overflow condition, FIFO_RST can be used to manually reset the
FIFO. However, the OC-48 transceiver has an automatic reset pin that will allow the FIFO to automatically
reset upon an Overflow condition. FIFO_AUTORST should be pulled "High" to enable the automatic FIFO
reset function.
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