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XRT91L82 View Datasheet(PDF) - Exar Corporation

Part Name
Description
MFG CO.
'XRT91L82' PDF : 59 Pages View PDF
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xr
REV. P1.0.5
PIN DESCRIPTIONS
PRELIMINARY
XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
COMMON CONTROL
NAME
LEVEL
RESET
LVTTL,
LVCMOS
TYPE
I
PIO_CFG1
LVTTL,
I
PIO_CFG0
LVCMOS
XRES1P
XRES1N
-
I
SE_REF
Analog
O
SEREFDIS
LVTTL,
I
LVCMOS
REF1CLKP LVPECL Diff
I
REF1CLKN
PIN
DESCRIPTION
E5 Master Reset Input
Active low signal. When this pin is pulled "Low" for more than
30ns, the internal registers are set to their default state. See
the register description for the default values.
This pin is provided with an internal pull-up.
D3 Parallel I/O Configuration
E3 Selects parallel I/O to be differential LVDS, differential
LVPECL, or Single-Ended LVPECL based on table below.
PIO_CFG
[1:0]
00
01
10
11
VDD_I/O
3.3V
3.3V
3.3V
Input
Configuration
Output
Configuration
3.3V
Differential
LVPECL
3.3V
Differential
LVPECL
3.3V
Single-Ended
LVPECL
3.3V
Single-Ended
LVPECL
3.3V
3.3V
Differential LVDS Differential LVDS
Reserved
This pin is provided with an internal pull-down.
E14 External LVDS Biasing Resistors
F14 A 402resistor with +/-1% tolerance should be placed across
these 2 pins for proper biasing. Although unecessary in
LVPECL operation, this resistor is required in LVDS operation.
See Figure 8 on page 22.
L7 Single-Ended LVPECL Biasing Output Reference
VBB 100K output bias reference.
Maximum load capacitance is 30pF. Maximum sourcing/sinking
capability is 750µA and 1000µA respectively.
C3 SE_REF Power down Control
Powers down SE_REF and reduces power consumption.
"Low" = SE_REF Enabled
"High" = SE_REF Disabled
This pin is provided with an internal pull-up.
A13 Reference Clock Input 1
B13 This differential clock input reference is used for the transmit
clock multiplier unit (CMU) and clock data recovery (CDR) to
provide the necessary high-speed clock reference for this
device. Pin REFREQSEL[1:0] determines the value used as
the reference. See Pin REFREQSEL[1:0] for more details.
Internally terminated and biased.
4
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